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| Number | Title | Issue Date |
| 8173491 | Standard cell architecture and methods with variable design rules Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum ... | 05/08/2012 |
| 8168479 | Resistance variable memory device and method of fabricating the same A method of fabricating a resistance variable device includes forming selection devices on a substrate, forming a conductive layer on the selection devices, patterning the conductive layer in a first direction to form conductive patterns spaced apart from each other... | 05/01/2012 |
| 8133765 | Integrated RF ESD protection for high frequency circuits The invention relates to a high-frequency integrated circuit requiring ESD protection for a circuit node. One or more metallic layer is deposited within the integrated circuit and patterned to form a transmission line. The metallic layers are generally already prese... | 03/13/2012 |
| 8105885 | Hardened programmable devices Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a... | 01/31/2012 |
| 8097498 | Damascene method of making a nonvolatile memory device A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rai... | 01/17/2012 |
| 8084303 | Semiconductor device and a method of manufacturing the same In a memory cell array on a main surface of a semiconductor substrate, a floating gate electrode for accumulating charges for information is arranged. The floating gate electrode is covered with a cap insulating film and a pattern of an first insulating film formed ... | 12/27/2011 |
| 8034668 | Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors,... | 10/11/2011 |
| 8021933 | Integrated circuit including structures arranged at different densities and method of forming the same A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures ar... | 09/20/2011 |
| 8012811 | Methods of forming features in integrated circuits A feature is formed in an integrated circuit by providing one or more layers to be patterned, providing a first layer overlying the one or more layers to be patterned, and providing a second layer overlying the first layer. The second layer is patterned to form a ra... | 09/06/2011 |
| 7951652 | Mask layout method, and semiconductor device and method for fabricating the same Provided are a mask layout method and a semiconductor device and a method for fabricating the same. The semiconductor device can include a main pattern, a first dummy pattern, and a second dummy pattern. The main pattern can be disposed on a substrate. The first dum... | 05/31/2011 |
| 7943436 | Integrated circuit devices and methods and apparatuses for designing integrated circuit devices Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment of the present invention, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling a... | 05/17/2011 |
| 7939384 | Eliminating poly uni-direction line-end shortening using second cut A method of forming an integrated circuit structure includes providing a substrate including a first active region and a second active region; forming a gate electrode layer over the substrate; and etching the gate electrode layer. The remaining portions of the gate... | 05/10/2011 |
| 7927926 | Non-volatile semiconductor storage device and method of manufacturing the same A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction t... | 04/19/2011 |
| 7915092 | Nonvolatile memory with a unified cell structure A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can... | 03/29/2011 |
| 7901999 | FPGA equivalent input and output grid muxing on structural ASIC memory The present invention provide circuits, methods, and apparatus directed to an integrated circuit having a memory interface that is configurable to have one of a multiple different bus widths. The memory interface has a first set of lines and a second set of lines. T... | 03/08/2011 |
| 7883940 | Ball grid array including redistribution layer, packaged integrated circuit including the same, and methods of making and using the same Method, algorithms, architectures, packages, circuits, and/or approaches for relatively low cost packaged integrated circuits (e.g., ball grid array or BGA packages) are disclosed. For example, a packaged integrated circuit can include a chip with a plurality of bon... | 02/08/2011 |
| 7858448 | Method of forming support structures for semiconductor devices Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The centra... | 12/28/2010 |
| 7851273 | Method of testing an integrated circuit die, and an integrated circuit die In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not... | 12/14/2010 |
| 7838342 | Memory device and method During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantial... | 11/23/2010 |
| 7833841 | Semiconductor apparatus and method for manufacturing the same The present invention is a method for manufacturing a semiconductor apparatus including a chip which is fabricated in large numbers on a wafer and has a plurality of information blocks. In the method, a unique information bit is written in a chip discrimination bloc... | 11/16/2010 |
| 7833842 | Mixed-scale electronic interface Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submi... | 11/16/2010 |
| 7795080 | Methods of forming integrated circuit devices using composite spacer structures Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a ... | 09/14/2010 |
| 7790516 | Method of manufacturing at least one semiconductor component and memory cells A method of manufacturing at least one NAND-coupled semiconductor component is disclosed. A layer structure is formed on or above a semiconductor substrate. The layer structure is patterned to expose at least one region to be doped. The exposed region is doped and a... | 09/07/2010 |
| 7781269 | Triangle two dimensional complementary patterning of pillars A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall s... | 08/24/2010 |
| 7767499 | Method to form upward pointing p-i-n diodes having large and uniform current A method is disclosed to form an upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top ... | 08/03/2010 |
| 7749816 | Systems and arrangements to interconnect components of a semiconductor device Systems and arrangements to interconnect cells and structures within cells of an integrated circuit to enhance cell density are disclosed. Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasi... | 07/06/2010 |
| 7745265 | Method of making three dimensional NAND memory A method of making a monolithic, three dimensional NAND string, includes forming a select transistor, forming a first memory cell over a second memory cell, forming a first word line for the first memory cell, forming a second word line for the second memory cell, f... | 06/29/2010 |
| 7736953 | Semiconductor memory and method of fabricating the same A semiconductor memory includes first and second source regions that are formed in a semiconductor substrate and run in orthogonal directions. The first and second source regions are diffused regions and are electrically connected to each other at crossing portions ... | 06/15/2010 |
| 7732261 | Semiconductor device and a method of manufacturing the same In a memory cell array on a main surface of a semiconductor substrate, a floating gate electrode for accumulating charges for information is arranged. The floating gate electrode is covered with a cap insulating film and a pattern of a first insulating film formed t... | 06/08/2010 |
| 7709301 | Integrated circuit having efficiently packed decoupling capacitors An integrated circuit includes a substrate having a semiconducting surface (605) and a plurality of standard cells arranged in a plurality of rows including at least a first row (610) and a second row (615) immediately above the first row. The f... | 05/04/2010 |
| 7709300 | Structure and method for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks A method and system for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks, or with other two-mask lithographic processes employing a trim mask. The method and system comprises locating regions in a finished semiconductor design t... | 05/04/2010 |
| 7704803 | Semiconductor device having diffusion layers as bit lines and method for manufacturing the same A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion ... | 04/27/2010 |
| 7696018 | Methods for fabricating multi-terminal phase change devices Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. T... | 04/13/2010 |
| 7682880 | Method and device for producing layout patterns of a semiconductor device having an even wafer surface Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell with a diffusion layer and no wiring, is arranged in the vacant areas ... | 03/23/2010 |
| 7678619 | Method of manufacturing a thin film transistor matrix substrate A method of manufacturing a thin film transistor matrix substrate is provided. The first photo-mask process is used to define a gate electrode and a signal electrode. The second photo-mask process is used to obtain different thickness of a PR layer in different regi... | 03/16/2010 |
| 7595229 | Configurable integrated circuit capacitor array using via mask layers A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitan... | 09/29/2009 |
| 7569428 | Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plur... | 08/04/2009 |
| 7553703 | Methods of forming an interconnect structure Semiconductor devices having conductive lines with extended ends and methods of extending conductive line ends by a variable distance are disclosed. An end of a first conductive feature of an interconnect structure is extended by a first distance, and an end of a se... | 06/30/2009 |
| 7494849 | Methods for fabricating multi-terminal phase change devices Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. T... | 02/24/2009 |
| 7427536 | High density stepped, non-planar nitride read only memory A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge storage regions in its nitride layer and a pair of source/drain regions that are shared with adjacent cells... | 09/23/2008 |
