Did You Know...
...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8187924 | Method, design program and design support device for semiconductor integrated circuit, and semiconductor integrated circuit A design method for a semiconductor integrated circuit, includes: a first calculating step; a second calculating step; and a setting step. The first step is a step of calculating a consumption current amount of a layout target circuit based on circuit information. T... | 05/29/2012 |
| 8178396 | Methods for forming three-dimensional memory devices, and related structures Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and clea... | 05/15/2012 |
| 8168478 | Method for producing a matrix of individual electronic components and matrix produced thereby The invention relates to a method for producing a matrix of electronic components, comprising a step of producing an active layer on a substrate, and a step of individualizing the components by forming trenches in the active layer at least until the substrate emerge... | 05/01/2012 |
| 8114716 | Deletable nanotube circuit Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions. ... | 02/14/2012 |
| 8114715 | Resistive random access memory and method for manufacturing the same A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first wi... | 02/14/2012 |
| 8114714 | Electronic device and production method thereof An object is to provide an electronic device of a multilayer structure with high density and high reliability that can be reduced in size while incorporating an electronic component therein, and further provide a production method for easily producing such an electr... | 02/14/2012 |
| 8105884 | Cross point memory arrays, methods of manufacturing the same, masters for imprint processes, and methods of manufacturing masters A cross point memory array includes a structure in which holes are formed in an insulating layer and a storage node is formed in each of the holes. The storage node may include a memory resistor and a switching structure. The master for an imprint process used to fo... | 01/31/2012 |
| 8043900 | Semiconductor integrated circuit device and a method of manufacturing the same To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large potential difference fro... | 10/25/2011 |
| 8017453 | Method and apparatus for forming an integrated circuit electrode having a reduced contact area A method and an apparatus for manufacturing a memory cell having a nonvolatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A rec... | 09/13/2011 |
| 8012810 | Low parasitic capacitance bit line process for stack DRAM A method of manufacturing low parasitic capacitance bit line for stack DRAM, comprising the following steps: offering a semi-conductor base, which semi-conductor having already included an oxide, plural word line stacks, plural bit line stacks and plural polysilicon... | 09/06/2011 |
| 8008134 | Large substrate structural vias An electronic package and methods by which the package reduces thermal fatigue failure of conductors in the electronic package. The electronic package includes a carrier substrate having first and second surfaces and a plurality of anchor vias having a via material ... | 08/30/2011 |
| 7972907 | Via configurable architecture for customization of analog circuitry in a semiconductor device A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elem... | 07/05/2011 |
| 7923305 | Patterning method for high density pillar structures A method of making a device includes forming a first sacrificial layer over an underlying layer, forming a first photoresist layer over the first sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photor... | 04/12/2011 |
| 7910407 | Quad memory cell and method of making same A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity ... | 03/22/2011 |
| 7871866 | Method of manufacturing semiconductor device having transition metal oxide layer and related device Provided is a method of manufacturing a semiconductor device having a switching device capable of preventing a snake current. First, a transition metal oxide layer and a leakage control layer are alternately stacked on a substrate 1 to 20 times to form a varistor la... | 01/18/2011 |
| 7867831 | Manufacturing method of flash memory device comprising gate columns penetrating through a cell stack A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer... | 01/11/2011 |
| 7846781 | Deletable nanotube circuit Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions. ... | 12/07/2010 |
| 7838341 | Self-aligned memory cells and method for forming The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from o... | 11/23/2010 |
| 7829391 | Active matrix substrate, method of making the substrate, and display device An active matrix substrate includes base substrate, gate lines, data lines, thin-film transistors and pixel electrodes. The gate lines are formed on the base substrate. The data lines are formed over the gate lines. Each of the data lines crosses all of the gate lin... | 11/09/2010 |
| 7820491 | Light erasable memory and method therefor A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of... | 10/26/2010 |
| 7807513 | Method for manufacturing semiconductor device Methods for manufacturing a semiconductor device are provided that reduces the thickness of an oxide layer formed on a polysilicon layer for bit line contacts. A reduced thickness oxide layer can prevent short circuits between adjoining bit lines. A reduced thicknes... | 10/05/2010 |
| 7799616 | Manufacturing method of flash memory device comprising gate columns penetrating through a cell stack A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer... | 09/21/2010 |
| 7781267 | Enclosed nanotube structure and method for forming A semiconductor device and associated method for forming. The semiconductor device comprises an electrically conductive nanotube formed over a first electrically conductive member such that a first gap exists between a bottom side the electrically conductive nanotub... | 08/24/2010 |
| 7781268 | Array substrate and display panel A manufacturing method for an array substrate, comprising forming a gate metal on a base substrate, patterning the gate metal to form a gate part having a gate electrode, a gate line and a gate pad. Then, a gate insulating layer, an active layer and a data metal are... | 08/24/2010 |
| 7776659 | Semiconductor device manufacturing method A method of manufacturing a semiconductor device having a first memory cell array region and a second memory cell array region, the method includes forming an active region on a surface layer of a semiconductor substrate, forming a first word line extending in a fir... | 08/17/2010 |
| 7754539 | Module integration integrated circuits An electronic module that operates at various radio frequency standards is provided. The module includes a first integrated circuit die formed in a first semiconductor substrate and manufactured using a first semiconductor process. Disposed within the first integrat... | 07/13/2010 |
| 7727820 | Misalignment-tolerant methods for fabricating multiplexing/demultiplexing architectures This disclosure relates to misalignment-tolerant processes for fabricating multiplexing/demultiplexing architectures. One process enables fabricating a multiplexing/demultiplexing architecture at a tolerance greater than a pitch of conductive structures with which t... | 06/01/2010 |
| 7709299 | Hierarchical 2T-DRAM with self-timed sensing An embodiment of the present invention is method of forming an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bi... | 05/04/2010 |
| 7709298 | Selectively altering a predetermined portion or an external member in contact with the predetermined portion A method for selectively altering a predetermined portion of an object or an external member in contact with the predetermined portion of the object is disclosed. The method includes selectively electrically addressing the predetermined portion, thereby locally resi... | 05/04/2010 |
| 7704802 | Programmable random logic arrays using PN isolation Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type,... | 04/27/2010 |
| 7696017 | Memory device with a selection element and a control line in a substantially similar layer The invention facilitates manufacture of semiconductor memory components by reducing the number of layers required to implement a semiconductor memory device. The invention provides for a selection element to be formed in the same layer as one of the control lines (... | 04/13/2010 |
| 7645644 | Data line layout in semiconductor memory device and method of forming the same In one aspect, a semiconductor device is provided which includes a data block including M parallel and sequentially arranged data lines numbered {0, 1, 2, . . . n, n+1, . . . , m−1, m}, where M, n and m are positive integers, and where n | 01/12/2010 |
| 7608488 | Semiconductor memory device and method of manufacturing the same A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device and a second semiconductor device wherein a cell array ratio is smaller than that of the first semiconductor device, said manufacturing method has forming the heig... | 10/27/2009 |
| 7585703 | Pixel control element selection transfer method, pixel control device mounting device used for pixel control element selection transfer method, wiring formation method after pixel control element transfer, and planar display substrate There is provided a method for selectively transferring pixel control devices onto a planar display substrate, which method enables prepared pixel control devices to be easily, reliably and inexpensively mounted without inducing any loss of pixel control devices. Th... | 09/08/2009 |
| 7556988 | Thin film transistor substrate of horizontal electric field type liquid crystal display device and fabricating method thereof A thin film transistor substrate of horizontal electric field type includes: a gate line and a first common line formed on a substrate to be in parallel to each other; a data line crossing the gate line and the first common line with a gate insulating film therebetw... | 07/07/2009 |
| 7550323 | Electrical fuse with a thinned fuselink middle portion A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semic... | 06/23/2009 |
| 7547584 | Method of reducing charging damage to integrated circuits during semiconductor manufacturing An integrated circuit die includes thereon a first device region, a second device region and a non-active region. A first implant mask, which covers the second device region and the non-active region, while exposing the first device region, is formed over the semico... | 06/16/2009 |
| 7541223 | Array substrate and liquid crystal display apparatus having the same In an array substrate and an LCD apparatus having the same, the array substrate includes a signal line, a first insulating layer formed on the signal line, and a pixel electrode formed on the first insulating layer and overlapped with the signal line. The pixel elec... | 06/02/2009 |
| 7531388 | Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum w... | 05/12/2009 |
| 7517736 | Structure and method of chemically formed anchored metallic vias Methods are provided that enable the ability to use a less aggressive liner processes, while producing structures known to give a desired high stress migration and electro-migration reliability. The present invention circumvents the issue of sputter damage of low k ... | 04/14/2009 |
