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| Number | Title | Issue Date |
| 8114713 | Method of manufacturing a lead frame with a nickel coating A lead frame includes a base material having a front surface for mounting of a semiconductor chip and a back surface for connection with an external board, and an Ni layer having a thick section and thin section. The thick section is formed on the back surface of th... | 02/14/2012 |
| 8105882 | Processing a memory request in a chip multiprocessor having a stacked arrangement A chip multiprocessor die supports optional stacking of additional dies. The chip multiprocessor includes a plurality of processor cores, a memory controller, and stacked cache interface circuitry. The stacked cache interface circuitry is configured to attempt to re... | 01/31/2012 |
| 8105881 | Method of fabricating chip package structure A method of fabricating a chip package structure includes the steps of providing a lead frame having a die pad, plural leads and at least one structure enhancement element. A chip is then disposed on the die pad and plural bonding wires are formed to electrically co... | 01/31/2012 |
| 8101469 | Method of forming monolithic CMOS-MEMS hybrid integrated, packaged structures A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one prot... | 01/24/2012 |
| 8097495 | Die package with asymmetric leadframe connection A leadframe for a semiconductor package is disclosed including electrical leads which extend from one side of the leadframe to an opposite side of the leadframe, where electrical connection may be made with the semiconductor die at the second side of the leadframe. ... | 01/17/2012 |
| 8097496 | Method of forming quad flat package A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Anoth... | 01/17/2012 |
| 8088650 | Method of fabricating chip package A method of fabricating a chip package is provided. A thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts are provided. A chip is disposed on the thin metal plate, and a plurality of bonding wires for e... | 01/03/2012 |
| 8080448 | Semiconductor device with nested rows of contacts A method of making semiconductor devices includes producing an array of first lead frames having rows of first electrical contact elements on respective sides. Sub-assemblies are produced by applying a first molding compound peripherally to provide support between t... | 12/20/2011 |
| 8076184 | Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die A semiconductor device has a base carrier with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base carrier. The first set of base leads can have a different height or similar heig... | 12/13/2011 |
| 8076183 | Method of attaching an interconnection plate to a semiconductor die within a leadframe package A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semic... | 12/13/2011 |
| 8067273 | Self locking and aligning clip structure for semiconductor die package A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip ali... | 11/29/2011 |
| 8067272 | Integrated circuit package system for package stacking and manufacturing method thereof A stackable multi-chip package system is provided including forming an external interconnect having a base and a tip, connecting a first integrated circuit die and the base, stacking a second integrated circuit die over the first integrated circuit die in an active ... | 11/29/2011 |
| 8067271 | Integrated circuit package system with encapsulation lock An integrated circuit package system is provided including forming an external interconnect and a tie bar, forming a lead tip and a lead body of the external interconnect, forming a hole in the external interconnect, forming a slot in the tie bar, connecting an inte... | 11/29/2011 |
| 8062934 | Integrated circuit package system with ground bonds An integrated circuit package system comprising: forming leads adjacent a die paddle having a die pad extension; forming a region having one of the leads depopulated for the die pad extension; and connecting an integrated circuit die to the die pad extension. ... | 11/22/2011 |
| 8058107 | Semiconductor die package using leadframe and clip and method of manufacturing A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major porti... | 11/15/2011 |
| 8053285 | Thermally enhanced single inline package (SIP) In a method and system for fabricating a thermally enhanced semiconductor device (200, 300) is packaged as a through hole single inline package (SIP). A leadframe (210, 310, 410) having a die pad (220, 320, 420) to attach an IC die (230, 330 | 11/08/2011 |
| 8048720 | Wire loop and method of forming the wire loop A method of forming a wire loop is provided. The method includes: (1) forming a first fold of wire; (2) bonding the first fold of wire to a first bonding location to form a first bond; (3) extending a length of wire, continuous with the first bond, between (a) the f... | 11/01/2011 |
| 8039318 | System and method for routing signals between side-by-side die in lead frame type system in a package (SIP) devices An integrated circuit includes a first and a second die positioned on a lead frame of a package. The lead frame includes a plurality of bond fingers. The integrated circuit includes a first bond pad on the first die that is electrically interconnected to a correspon... | 10/18/2011 |
| 8039317 | Aluminum leadframes for semiconductor QFN/SON devices A post-mold plated semiconductor device has an aluminum leadframe (105) with a structure including a chip mount pad and a plurality of lead segments without cantilevered lead portions. A semiconductor chip (210) is attached to the chip mount pad, and c... | 10/18/2011 |
| 8026130 | Method for manufacturing a semiconductor integrated circuit device A method is provided for manufacturing a QFN type semiconductor integrated circuit device using a multi-device lead frame having a tie bar for tying external end portions of plural leads, wherein sealing resin filled between an outer periphery of a mold cavity and t... | 09/27/2011 |
| 8021929 | Apparatus and method configured to lower thermal stresses An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arr... | 09/20/2011 |
| 8021928 | System and method for routing supply voltages or other signals between side-by-side die and a lead frame for system in a package (SIP) devices An integrated circuit or chip includes a first die and a second die positioned on a lead frame of a package including a lead frame, such as a QFP, DIP, PLCC, TSOP, or any other type of package including a lead frame. The integrated circuit further includes a redistr... | 09/20/2011 |
| 8017446 | Method for manufacturing a rigid power module suited for high-voltage applications Method for manufacturing a rigid power module with a layer that is electrically insulating and conducts well thermally and has been deposited as a coating, the structure having sprayed-on particles that are fused to each other, of at least one material that is elect... | 09/13/2011 |
| 8017445 | Warpage-compensating die paddle design for high thermal-mismatched package construction A method and packaging for semiconductor devices and integrated circuits is disclosed that eliminates warpage stress on packages caused by coefficient of thermal expansion (CTE) mismatch between the device, lead frame or die paddle and a molding compound. Generally,... | 09/13/2011 |
| 8017447 | Laser process for side plating of terminals A method of preparing a portion of the side of a terminal of an Integrated Circuit (IC) package for solder is disclosed. The method comprises the steps of attaching an IC die to a leadframe comprising a connecting bar, reducing the thickness of a portion of the conn... | 09/13/2011 |
| 8008132 | Etched surface mount islands in a leadframe package A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package includes a leadframe and one or more semiconductor die affixed to a die paddle of the leadframe. The leadframe is fo... | 08/30/2011 |
| 8003443 | Non-leaded integrated circuit package system with multiple ground sites A non-leaded integrated circuit package system is provided providing a die paddle of a lead frame, forming a dual row of terminals including an outer terminal and an inner terminal, and selectively fusing an inner terminal and an adjacent inner terminal to form a fu... | 08/23/2011 |
| 8003444 | Semiconductor device and manufacturing method thereof A method of manufacturing a semiconductor device 28 in which a plating mask 38, 39 having a noble metal plating layer 35 as an uppermost layer is formed at a predetermined portion on an obverse surface side or a reverse surface side of a leadfra... | 08/23/2011 |
| 8003447 | Multi-chip module for battery power control A multi-chip module suitable for use in a battery protection circuit. The multi-chip module includes an integrated circuit chip, a first power transistor, a second power transistor, a first connection structure electrically coupling the integrated circuit chip to th... | 08/23/2011 |
| 8003445 | Integrated circuit packaging system with z-interconnects having traces and method of manufacture thereof A method of manufacture of an integrated circuit packaging system includes: providing a carrier; mounting an integrated circuit on the carrier; mounting a z-interconnect on the carrier, the z-interconnect for supporting a trace cantilevered over the integrated circu... | 08/23/2011 |
| 8003446 | Flexible diode package and method of manufacturing A single step packaging process that both melts a solder and also cures an adhesive about a microelectronic circuit. The process finds technical advantages by simplifying packaging of a die that may be coupled to a planar flexible lead, which leads to a lower produc... | 08/23/2011 |
| 7998794 | Resin molded semiconductor device and manufacturing method thereof This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin mold... | 08/16/2011 |
| 7998795 | Method of manufacturing a semiconductor device including plural semiconductor chips A method for manufacturing a semiconductor device includes mounting a first chip over a first area of a chip mounting section of a lead frame and mounting a second chip over a second area of the chip mounting section, wherein the second area is adjacent to the first... | 08/16/2011 |
| 7993979 | Leadless package system having external contacts A leadless package system includes: providing a chip carrier having indentations defining a pattern for a protrusion for external contact terminals; placing an external coating layer in the indentations in the chip carrier; layering a conductive layer on top of the ... | 08/09/2011 |
| 7993980 | Lead frame, electronic component including the lead frame, and manufacturing method thereof A lead frame of the present invention includes: a die pad on which a device is mounted; a first connection terminal which is provided around the die pad, and the lower surface of which serves as an external terminal; a second connection terminal which is provided ar... | 08/09/2011 |
| 7989267 | Manufacturing method of semiconductor device and manufacturing method of lead frame Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding is performed, at the temperature 160 to 300° C. (preferably 180 to 300° C.) for a total of more than 2 mi... | 08/02/2011 |
| 7981729 | Fabrication method of multi-chip stack structure A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe ... | 07/19/2011 |
| 7955902 | Manufacturing method of semiconductor device with surface mounting terminals A semiconductor device manufacturing method in which a semiconductor chip is connected to first and second lead frames. Source and gate electrodes extending over a first main surface of the semiconductor chip are connected to first electrode plates of the first lead... | 06/07/2011 |
| 7955901 | Method for producing a power semiconductor module comprising surface-mountable flat external contacts A method for producing a power semiconductor module having surface mountable flat external contact areas is disclosed. At least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the side ... | 06/07/2011 |
| 7951651 | Dual flat non-leaded semiconductor package A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupl... | 05/31/2011 |
