Celebrity Inventors
Magician Harry Houdini patented a "Diver's Suit" enabling the wearer to "quickly divest himself of the suit while being submerged and to safely escape and reach the surface of the water."
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8148206 | Package for high power integrated circuits and method for forming A method for packaging an integrated circuit comprises the steps of: providing a ground plane, the ground plane having a recessed area shaped to receive an integrated circuit die, wherein the integrated circuit die having a first surface with active circuitry, a sec... | 04/03/2012 |
| 8119456 | Bond pad for wafer and package for CMOS imager An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seat between the bond pad region and an active circuit region, and includes... | 02/21/2012 |
| 8101468 | Method of manufacturing a semiconductor device The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor compo... | 01/24/2012 |
| 8101467 | Liquid crystal display device and method for manufacturing the same, and liquid crystal television receiver At least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask for forming a predetermined pattern is formed by a method capable of selectively forming a pattern to manufacture... | 01/24/2012 |
| 8062932 | Compact semiconductor package with integrated bypass capacitor and method A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous... | 11/22/2011 |
| 8048719 | Semiconductor device and manufacturing method thereof A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is hi... | 11/01/2011 |
| 8043898 | Method of manufacturing semiconductor package with etch removal of carrier frame and base plating layer A method of manufacturing a semiconductor package is provided, which can improve the quality of plating through reduction of plating deviation, and improve molding and soldering efficiencies in forming a molding compound and packaging the semiconductor package onto ... | 10/25/2011 |
| 8034665 | Microelectronic package with thermal access A method of forming a microelectronic package including the steps of providing a three-layer metal plate, having a first layer, a second layer and a third layer. A plurality of conductive elements is formed from the first layer of the metal plate. A dielectric sheet... | 10/11/2011 |
| 8021926 | Methods for forming semiconductor devices with low resistance back-side coupling Electronic elements (40) with very low resistance back-side coupling are provided by forming one or more narrow trenches or pipes (411), preferably dielectric lined, in front sides (523) of substrates (52′), filling the trenches or pipe... | 09/20/2011 |
| 8021925 | Thermal paste containment for semiconductor modules A semiconductor module structure and a method of forming the semiconductor module structure are disclosed. The structure incorporates a die mounted on a substrate and covered by a lid. A thermal compound is disposed within a thermal gap between the die and the lid. ... | 09/20/2011 |
| 7955899 | Method for providing and removing discharging interconnect for chip-on-glass output leads and structures thereof Microelectronic devices may be fabricated while being protected from damage by electrostatic discharge. In one embodiment, a shorting circuit is connected to elements of the microelectronic device, where the microelectronic device is part of a chip-on-glass system. ... | 06/07/2011 |
| 7947533 | Void free soldering semiconductor chip attachment method for wafer scale chip size Methods for attaching the wafer scale semiconductor chip, up to 4 square inch (2×2 inchs), are comprises of following steps. Stack assembles following materials from bottom to top. First lower integrated heat spreader (IHS). Second thermal interface material (TIM).... | 05/24/2011 |
| 7939377 | Method of manufacturing semiconductor element mounted wiring board A semiconductor element sealed substrate including a semiconductor element covered by an insulating layer is fabricated while a wiring substrate formed by stacking wiring layers is fabricated by a process different from the process of fabricating the semiconductor e... | 05/10/2011 |
| 7923299 | Manufacturing process for embedded semiconductor device A manufacturing process for an embedded semiconductor device is provided. In the manufacturing process, at least one insulation layer and a substrate are stacked to each other, and a third metal layer is laminated on the insulation layer to embed a semiconductor dev... | 04/12/2011 |
| 7906375 | Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates A semiconductor package is disclosed for packaging two adjacent semiconductor dies atop a circuit substrate. The dies are separated from each other along their longitudinal edges with an inter-die distance. An elevation-adaptive electrical connection connects a top ... | 03/15/2011 |
| 7906374 | COF packaging structure, method of manufacturing the COF packaging structure, and method for assembling a driver IC and the COF packaging structure thereof A COF packaging structure includes a substrate, a first conductive foil, and a second conductive foil. The substrate has a first surface and a second surface opposite to the first surface. The first conductive foil is disposed on the first surface of the substrate a... | 03/15/2011 |
| 7879651 | Packaging conductive structure and method for forming the same A packaging conductive structure for a semiconductor substrate and a method for forming the structure are provided. The dielectric layer of the packaging conductive structure partially overlays the metallic layer of the semiconductor substrate and has a receiving sp... | 02/01/2011 |
| 7851267 | Power semiconductor module method A method for assembling a power module includes providing a casing with a plurality of receiving elements. At least one substrate carrying at least one semiconductor chip is provided within the casing. At least one support element is provided. An elastically stresse... | 12/14/2010 |
| 7846777 | Semiconductor device package and fabricating method thereof A semiconductor device package and fabricating method thereof are disclosed, by which heat-dissipation efficiency is enhanced in a system by interconnection (SBI) structure. An exemplary semiconductor device package may include a substrate, at least two chips mounte... | 12/07/2010 |
| 7842552 | Semiconductor chip packages having reduced stress A structure and a method for forming the same. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coeffi... | 11/30/2010 |
| 7829387 | Electronic apparatus and method of manufacturing the same An electronic apparatus includes metal wiring plates placed together in the same plane to provide a wiring circuit, electronic devices mounted to the wiring plates through a solder, a case having a base portion and columnar portions extending from the base portion. ... | 11/09/2010 |
| 7799613 | Integrated module for data processing system An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the p... | 09/21/2010 |
| 7790510 | Metal lid with improved adhesion to package substrate A metal lid for packaging semiconductor chips is stamped to form a sloped sidewall with a set-back from the edge of a package substrate. After the metal lid is placed over the semiconductor chip, molding compound is formed around portions of the exposed perimeter of... | 09/07/2010 |
| 7776658 | Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates A semiconductor package is disclosed for packaging two adjacent semiconductor dies atop a circuit substrate. The dies are separated from each other along their longitudinal edges with an inter-die distance. An elevation-adaptive electrical connection connects a top ... | 08/17/2010 |
| 7682876 | Electronic assemblies having a low processing temperature Embodiments relate to electronic assemblies and methods for forming electronic assemblies. One method includes providing a die and a copper heat spreader that are to be coupled to one another through a thermal interface material. A layer of tin is formed on the copp... | 03/23/2010 |
| 7459345 | Packaging method for an electronic element A packaging method for an electronic element has: etching portions of a top surface of a metal board to form recesses between raised unetched segments and filling the recesses with a dielectric material of high density polymer; forming multiple solder balls respecti... | 12/02/2008 |
| 7443002 | Encapsulated microstructure and method of producing one such microstructure A microstructure including in a first layer insulated from a substrate by an insulator layer at least one sensitive element connected to at least one contact pad by an electrical connection and protected by a package cap. The sensitive element, the electrical connec... | 10/28/2008 |
| 7429501 | Lid and method of employing a lid on an integrated circuit A lid having a plurality of recesses at the edges of the lid to provide an improved adhesive bond between the lid and a substrate of an integrated circuit is disclosed. The plurality of recesses may be a castellation comprising a collection of semi-circular cuts int... | 09/30/2008 |
| 7425469 | Method for encapsulating an electronic component using a foil layer The invention relates to a method for encapsulating an electronic component, in particular a semiconductor, fixed on a carrier, comprising the processing steps of: a) placing at least one foil layer in a mould, b) placing the carrier in contact with the foil layer w... | 09/16/2008 |
| 7423342 | Method for assembling semiconductor switching elements and heat sink in rotary electric machine and rotary electric machine A method for assembling semiconductor switching elements and a heat sink in a rotary electric machine includes: a first step in which bare chips of the semiconductor switching elements are bonded to the heat sink using a good heat conductive bonding material; a seco... | 09/09/2008 |
| 7414663 | Imaging element, imaging device, camera module and camera system The method for manufacturing a camera module of the present invention includes forming a bump on each electrode portion of an imaging element. Next, a through hole is formed in a substrate. The imaging element is then mounted on a first side of the substrate having ... | 08/19/2008 |
| 7410886 | Method for fabricating protective caps for protecting elements on a wafer surface A method of fabricating protective caps for protecting devices on wafer surface includes: (a) providing a non-metal cap substrate and forming a metal layer on the non-metal cap substrate; (b) forming a plurality of cavities on a surface of the metal layer, wherein t... | 08/12/2008 |
| 7405106 | Quad flat no-lead chip carrier with stand-off A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second le... | 07/29/2008 |
| 7402462 | Folded frame carrier for MOSFET BGA A folded frame carrier has a die attach pad (DAP) 30 and one or more folded edges 32, 33, 34, 35. Each folded edge has one or more studs 36 and each stud has a trapezoidal tip. The folded frame carrier may be made of single gauge copper or coppe... | 07/22/2008 |
| 7388295 | Multi-chip module A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for ... | 06/17/2008 |
| 7381593 | Method and apparatus for stacked die packaging A method and apparatus for stacked die packaging provide a leadframe configured for supporting a lower semiconductor die. At least one pillar is formed on the leadframe for supporting an upper semiconductor die. The pillar is formed integrally with and of the same m... | 06/03/2008 |
| 7374969 | Semiconductor package with conductive molding compound and manufacturing method thereof The present invention relates to a semiconductor package having a conductive molding compound to prevent static charge accumulation. By using a conductive molding compound heat conductivity is also increased and heat generated by the semiconductor chip is more effec... | 05/20/2008 |
| 7372133 | Microelectronic package having a stiffening element and method of making same A method of forming a leadframe package, a leadframe package formed according to the method, and a system incorporating the leadframe package. The leadframe package includes: a metallization layer comprising a paddle portion and a contact portion including contact l... | 05/13/2008 |
| 7371682 | Production method for electronic component and electronic component A method of manufacturing an electronic part in which on the upper surface of an insulating member covering lower layer wiring, a conductor portion connected from the lower layer wiring is exposed. In this method, electric power supplying film is formed on the upper... | 05/13/2008 |
| 7372138 | Routing element for use in multi-chip modules, multi-chip modules including the routing element and methods A routing element for use in a semiconductor device assembly includes a substrate that carries conductive traces that provide either additional electrical paths or shorter electrical paths than those provided by a carrier substrate of the semiconductor device assemb... | 05/13/2008 |
