Bizarre Patents
Decorative Jeweled Wheel Cover
An improved wheel is provided wherein decorative items such as gem stones are embedded in either the wheel surface, a special mounting section attached to the wheel surface, or to a spoke strap that wraps around each spoke and positions embedded gem stones on the outside surface of the spoke.
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| Number | Title | Issue Date |
| 8137995 | Double-sided semiconductor device and method of forming top-side and bottom-side interconnect structures A semiconductor device is made by forming a first active device on a first side of a semiconductor wafer. A first insulating layer is formed over the first side of the wafer. A first conductive layer is formed over the first insulating layer. A first interconnect st... | 03/20/2012 |
| 7993938 | Highly doped III-nitride semiconductors A method of forming a highly doped layer of AlGaN, is practiced by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN... | 08/09/2011 |
| 7795046 | Method and apparatus for monitoring endcap pullback Various apparatus and methods of monitoring endcap pullback are disclosed. In one aspect, an apparatus is provided that includes a substrate that has a plurality of semiconductor regions. Each of the plurality of semiconductor regions has a border with an insulating... | 09/14/2010 |
| 7421358 | Method and system for measurement data evaluation in semiconductor processing by correlation-based data filtering By performing a contingency-based correlation test of measurement data, such as defect data, with respect to electrical test data after progressively filtering the measurement data, an enhanced analysis of process flow characteristics may be accomplished. Consequent... | 09/02/2008 |
| 7399657 | Ball grid array packages with thermally conductive containers Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the container by thermally conductive supports formed in the container or at... | 07/15/2008 |
| 7396760 | Method and system for reducing inter-layer capacitance in integrated circuits The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so ... | 07/08/2008 |
| 7395518 | Back end of line clone test vehicle A test vehicle comprises at least one product layer having a east one product circuit pattern on the product layer, and one or more clone layers formed over the product layer (1902). The one or more clone layers include a plurality of structures, which may in... | 07/01/2008 |
| 7384804 | Method and apparatus for electronically aligning capacitively coupled mini-bars One embodiment of the present invention provides a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation,... | 06/10/2008 |
| 7378288 | Systems and methods for producing light emitting diode array Systems and methods are disclosed for producing vertical LED array on a metal substrate; evaluating said array of LEDs for defects; destroying one or more defective LEDs; forming good LEDs only LED array suitable for wafer level package. ... | 05/27/2008 |
| 7378290 | Isolation circuit An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third p... | 05/27/2008 |
| 7338817 | Body bias compensation for aged transistors Embodiments of the invention include on-chip transistor degradation detection and compensation. In one embodiment of the invention, an integrated circuit is provided including a circuit with a body bias terminal coupled to a body of one or more transistors to receiv... | 03/04/2008 |
| 7332924 | Embedded test circuitry and a method for testing a semiconductor device for breakdown, wearout or failure Reliability testing circuitry is built into the wafer or IC package in the form of one or more individual testers that use small-area transistors as DUTs. Stress can be applied to the DUTs in parallel and information about breakdown, wearout or failure can be obtain... | 02/19/2008 |
| 7300827 | Method of manufacturing a thin film transistor substrate and stripping composition A method of manufacturing a thin film transistor substrate includes forming a transistor thin layer pattern, forming a protecting layer, forming a photoresist film, forming a pixel electrode and a conductive layer that are separated from each other, stripping a phot... | 11/27/2007 |
| 7292742 | Waveguides for performing enzymatic reactions The present invention is directed to a method and an apparatus for analysis of an analyte. The method involves providing a zero-mode waveguide which includes a cladding surrounding a core where the cladding is configured to preclude propagation of electromagnetic en... | 11/06/2007 |
| 7242075 | Silicon wafers and method of fabricating the same By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. ... | 07/10/2007 |
| 7241635 | Binning for semi-custom ASICs A binning method is disclosed for measuring semiconductor devices for certain parameters and placing specific devices into different categories or “bins” according to the measured parameters. Measurable parameters include performance/speed-grading, power consump... | 07/10/2007 |
| 7236847 | Systems and methods for closed loop defect reduction Systems and methods for repairing defects on a specimen are provided. A method may include processing a specimen, detecting defects on the specimen, and repairing one or more of the defects. An additional method may include detecting defects on a specimen, repairing... | 06/26/2007 |
| 7229845 | Automated sourcing of substrate microfabrication defects using defects signatures Automated defect sourcing system identifies root-causes of yield excursion due to contamination, process faults, equipment failure and/or handling in timely manner and provides accurate timely feedback to address and contain the sources of yield excursion. A signatu... | 06/12/2007 |
| 7226854 | Methods of forming metal lines in semiconductor devices Methods of forming metal lines in semiconductor devices are disclosed. One example method may include forming lower metal lines and forming an insulation layer on the lower metal lines; etching said insulation layer to a depth; and depositing a material for upper me... | 06/05/2007 |
| 7220603 | Method for manufacturing display device and manufacturing apparatus It is an object of the present invention to provide a method of manufacturing a display device, which can display images favorably by insulating a short-circuit portion between an anode and a cathode. Further, it is another object of the invention to provide a metho... | 05/22/2007 |
| 7214549 | Correcting device, exposure apparatus, device production method, and device produced by the device production method A correcting device that properly maintains the flatness of a mask, an exposure apparatus in which overlay accuracy is increased by making use of the correcting device, and a device production method. The correcting device includes a gas flow path including a first ... | 05/08/2007 |
| 7205566 | Transistor-level signal cutting method and structure A modifiable circuit structure and its method of formation are disclosed. The modifiable circuit structure electrically couples one portion of an interconnect with another portion of the interconnect through vias disposed in a dielectric layer. The combination of th... | 04/17/2007 |
| 7198963 | Methodologies for efficient inspection of test structures using electron beam scanning and step and repeat systems Disclosed are techniques for efficiently inspecting defects on voltage contrast test. In one embodiment, methodologies and test structures allow inspection to occur entirely within a charged particle system. In a specific embodiment, a method of localizing and imagi... | 04/03/2007 |
| 7182794 | Correcting device, exposure apparatus, device production method, and device produced by the device production method A correcting device that properly maintains the flatness of a mask, an exposure apparatus in which overlay accuracy is increased by making use of the correcting device, and a device production method. The correcting device includes a gas flow path including a first ... | 02/27/2007 |
| 7181122 | Zero-mode waveguides The present invention is directed to a method and an apparatus for analysis of an analyte. The method involves providing a zero-mode waveguide which includes a cladding surrounding a core where the cladding is configured to preclude propagation of electromagnetic en... | 02/20/2007 |
| 7153709 | Method and apparatus for calibrating degradable components using process state data The present invention is generally directed to various methods and systems for calibrating degradable components using process state data. In one illustrative embodiment, the method includes providing a tool comprised of at least one process chamber, providing at le... | 12/26/2006 |
| 7141439 | Transistor-level signal cutting method and structure A modifiable circuit structure and its method of formation are disclosed. The modifiable circuit structure electrically couples one portion of an interconnect with another portion of the interconnect through vias disposed in a dielectric layer. The combination of th... | 11/28/2006 |
| 7138282 | Correcting device, exposure apparatus, device production method, and device produced by the device production method A correcting device that properly maintains the flatness of a mask, an exposure apparatus in which overlay accuracy is increased by making use of the correcting device, and a device production method. The correcting device includes a gas flow path including a first ... | 11/21/2006 |
| 7125729 | Method for opening the plastic housing of an electronic module In a method of opening of a housing of a plastic-housed electronic module by a laser, the electronic module is protected from the effects of the laser beam and the laser beam is stopped at a suitable time by providing an end point signal detection due to the laser b... | 10/24/2006 |
| 7111629 | Method for cleaning substrate surface There is provided a surface cleaning apparatus and method using plasma to remove a native oxide layer, a chemical oxide layer, and a damaged portion from a silicon substrate surface, and contaminants from a metal surface. A mixture of H2 and N2 | 09/26/2006 |
| 7105877 | Conductive line structure A conductive line Structure. In one embodiment of the invention, a conductive line includes at least two outer conductive portions, an inner conductive portion between the outer conductive portions, separated from the outer conductive portions by at least two trench... | 09/12/2006 |
| 7107158 | Inspection system and apparatus A method and system for identifying a defect or contamination on a surface of a sample. The system operates by detecting changes in work function across a surface via both vCPD and nvCPD. It utilizes a non-vibrating contact potential difference (nvCPD) sensor for im... | 09/12/2006 |
| 7103482 | Inspection system and apparatus A method and system for identifying a defect or contamination on a surface of a material. The method and system involves providing a material, such as a semiconductor wafer, using a non-vibrating contact potential difference sensor to scan the wafer, generate contac... | 09/05/2006 |
| 7098047 | Wafer reuse techniques Briefly, test wafer reuse techniques. ... | 08/29/2006 |
| 7092826 | Semiconductor wafer inspection system A method and system for identifying a defect or contamination on a surface of a material. The method and system involves providing a material, such as a semiconductor wafer, using a non-vibrating contact potential difference sensor to scan the wafer, generate contac... | 08/15/2006 |
| 7069155 | Real time analytical monitor for soft defects on reticle during reticle inspection The present invention generally relates to semiconductor processing, and in particular to methods and systems for analyzing photolithographic reticle defects that include detecting soft defects on a reticle and analyzing the material composition of the defects for a... | 06/27/2006 |
| 7067335 | Apparatus and methods for semiconductor IC failure detection An improved voltage contrast test structure is disclosed. In general terms, the test structure can be fabricated in a single photolithography step or with a single reticle or mask. The test structure includes substructures which are designed to have a particular vol... | 06/27/2006 |
| 7043830 | Method of forming conductive bumps A sealing layer is provided on the surface of a substrate such as a semiconductor wafer. The sealing layer includes apertures which expose external contact locations for semiconductor dice formed on the wafer. Solder paste is deposited in the apertures and reflowed ... | 05/16/2006 |
| 7033843 | Semiconductor manufacturing method and semiconductor manufacturing apparatus A semiconductor manufacturing method whereby reactive gas processing such as selective epitaxial growth can be carried out with high precision by correctly adjusting conditions during processing is performed by a semiconductor manufacturing apparatus which can restr... | 04/25/2006 |
| 7013222 | Wafer edge inspection data gathering A wafer edge inspection method and apparatus include a review tool that captures images of the semiconductor wafer. According to various embodiments, the present invention also includes a map of points of interest proximate to the edge of the wafer, automatic image ... | 03/14/2006 |
