Class 438/109 - Stacked array (e.g., rectifier, etc.)

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making a semiconductor device wherein a multiplicity
No. of patents: 1203
Last issue date: 05/29/2012

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Number	Title	Issue Date
8187921	Semiconductor package having ink-jet type dam and method of manufacturing the same A semiconductor package includes a substrate which includes a chip mounting unit disposed on a first surface thereof and a pad forming unit disposed on an outer region of the chip mounting unit. The semiconductor package further includes a plurality of pads disposed...	05/29/2012
8183090	Methods for manufacturing device mounting board and circuit substrate To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate co...	05/22/2012
8163600	Bridge stack integrated circuit package-on-package system A bridge stack integrated circuit package-on-package system is provided including forming a first integrated circuit package system having a first substrate, forming a second integrated circuit package system having a second substrate, and mounting a bridge integrat...	04/24/2012
8158456	Method of forming stacked dies The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to metallization processing. TSVs may be fabricated with increased aspect ratio, extending deeper in a wa...	04/17/2012
8158457	Rule-based semiconductor die stacking and bonding within a multi-die package A rule-based method of optimizing wire bonding jumps is disclosed which minimizes the amount of wire used for wire bonds and/or minimizes a number of power and ground pads on a substrate to support all wired connections. ...	04/17/2012
8148202	Integrated circuit chip with smart pixels that supports through-chip electromagnetic communication One embodiment of the present invention provides an integrated circuit chip, including an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The integrated circuit chip additionally comprises an electromagnetic ...	04/03/2012
8143101	Semiconductor package and the method of making the same The present invention relates to semiconductor package and the method of making the same. The method of the invention comprises the following steps: (a) providing a first substrate; (b) mounting a first chip onto a surface of the first substrate; (c) forming a plura...	03/27/2012
8143102	Integrated circuit package system including die having relieved active region An integrated circuit package system includes: providing a substrate; attaching a base die to the substrate, the base die having a relief region with a shaped cross-section; and connecting a bond wire between an active base surface of the base die and the substrate,...	03/27/2012
8143103	Package stacking system with mold contamination prevention and method for manufacturing thereof A method for manufacturing a package stacking system includes: providing a package substrate; mounting an integrated circuit over the package substrate; forming a step-down interposer over the integrated circuit; and molding a stack package body, having a step profi...	03/27/2012
8143104	Method for manufacturing ball grid array package stacking system A method for manufacturing a ball grid array package stacking system includes: providing a base substrate; coupling an integrated circuit to the base substrate; coupling a stacking substrate over the base substrate; mounting a heat spreader, having an access port, a...	03/27/2012
8143100	Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages A method for making a semiconductor multi-package module includes; providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interc...	03/27/2012
8138022	Method of manufacturing semiconductor device A first conductive member made of metal is provided over a first wiring substrate, which is a mounting substrate in the lower tier, a through hole is provided in a second wiring substrate, which is a mounting substrate in the upper tier, at a position corresponding ...	03/20/2012
8124452	Processes and structures for IC fabrication The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete com...	02/28/2012
8124451	Integrated circuit packaging system with interposer An integrated circuit packaging system comprising: fabricating an interposer array having an access opening; fabricating a base package substrate sheet; attaching a first integrated circuit die over the base package substrate sheet; mounting the interposer array ove...	02/28/2012
8124453	Vertically packaged MOSFET and IC power devices as integrated module using 3D interconnected laminates An electronic package for containing at least a top packaging module vertically stacked on a bottom packaging module. Each of the packaging modules includes a semiconductor chip packaged and connected by via connectors and connectors disposed on a laminated board fa...	02/28/2012
8114708	System and method for pre-patterned embedded chip build-up A system and method for forming an embedded chip package is disclosed. The embedded chip package includes a first chip portion having a plurality of pre-patterned re-distribution layers joined together to form a pre-patterned lamination stack, with the pre-patterned...	02/14/2012
8110440	Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure A semiconductor device is made by forming first and interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structure...	02/07/2012
8101460	Semiconductor device and method of shielding semiconductor die from inter-device interference A plurality of stacked semiconductor wafers each contain a plurality of semiconductor die. The semiconductor die each have a conductive via formed through the die. A gap is created between the semiconductor die. A conductive material is deposited in a bottom portion...	01/24/2012
8101459	Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween A method for assembling semiconductor devices includes providing a first semiconductor device, securing spacers to noncircuit bond pads of the first semiconductor device, and positioning a second semiconductor device on the spacers. Adhesive material may be applied ...	01/24/2012
8101461	Stacked semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device includes: (a) half-dicing a semiconductor wafer including plural semiconductor chips, thereby forming dicing grooves in the semiconductor wafer, wherein each semiconductor chip includes a circuit and pads and wherein ...	01/24/2012
8093102	Process of forming an electronic device including a plurality of singulated die An electronic device can include a first die having a first terminal at a first front side, and a second die having a second terminal at a second front side and a through via. In one aspect, a process of forming the electronic device includes supplying a second subs...	01/10/2012
8093103	Multiple chip module and package stacking method for storage devices Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package ...	01/10/2012
8088648	Method of manufacturing a chip stack package A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetra...	01/03/2012
8080446	Integrated circuit packaging system with interposer interconnections and method of manufacture thereof A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing st...	12/20/2011
8067268	Stacked integrated circuit package system and method for manufacturing thereof A method for manufacturing of a stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit...	11/29/2011
8062929	Semiconductor device and method of stacking same size semiconductor die electrically connected through conductive via formed around periphery of the die A semiconductor device has a plurality of similar sized semiconductor die each with a plurality of bond pads formed over a surface of the semiconductor die. An insulating layer is formed around a periphery of each semiconductor die. A plurality of conductive THVs is...	11/22/2011
8058101	Microelectronic packages and methods therefor A method of making a microelectronic assembly includes providing a microelectronic package having a substrate, a microelectronic element overlying the substrate and at least two conductive elements projecting from a surface of the substrate, the at least two conduct...	11/15/2011
8058102	Package structure and manufacturing method thereof The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes a dielectric layer on a backside surface of the el...	11/15/2011
8053278	Multi-chip package type semiconductor device A multi-chip package type semiconductor device includes an insulating substrate having first and second conductive patterns thereon, a first semiconductor chip on the insulating substrate and having a first terminal pad and a relay pad isolated from the first termin...	11/08/2011
8048717	Method and system for bonding 3D semiconductor devices A method and system and for fabricating 3D (three-dimensional) SIC (stacked integrated chip) semiconductor devices. The system includes a vacuum chamber, a vacuum-environment treatment chamber, and a bonding chamber, though in some embodiments the same physical encl...	11/01/2011
8043895	Method of fabricating stacked assembly including plurality of stacked microelectronic elements A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like microelectronic elements attached together at dicing lanes. Each micr...	10/25/2011
8043894	Integrated circuit package system with redistribution layer An integrated circuit package system includes forming a first external interconnect having both a first side and a second side that is an opposing side to the first side; forming a first encapsulation around a first integrated circuit and the first external intercon...	10/25/2011
8039309	Systems and methods for post-circuitization assembly A method of making integrated circuit packages using a conductive plate as a substrate includes forming a partial circuit pattern on one side of the conductive plate by stamping or selectively removing a portion of the conductive plate through part of its thickness,...	10/18/2011
8034662	Thermal interface material with support structure Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface mat...	10/11/2011
8030135	Methods for a multiple die integrated circuit package Methods for a multiple die package for integrated circuits are disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and ele...	10/04/2011
8030134	Stacked semiconductor package having adhesive/spacer structure and insulation Stacked semiconductor assemblies in which a first die is mounted active side upward on a first substrate and is electrically interconnected to the substrate by wire bonding; an adhesive/spacer structure is formed upon the active side of the first die; and a device s...	10/04/2011
8026129	Stacked integrated circuits package system with passive components A stacked integrated circuit package system is provided forming a first stack layer having a first integrated circuit die on a first substrate, forming a second stack layer having a second integrated circuit die on a second substrate, and mechanically and electrical...	09/27/2011
8021923	Semiconductor package having through-hole vias on saw streets formed with partial saw A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer having a plurality of die with contact pads disposed on a surface of each die. The semiconductor wafer has a saw street between each die. A trench is formed in the ...	09/20/2011
8021924	Encapsulant cavity integrated circuit package system and method of fabrication thereof A method for fabricating an encapsulant cavity integrated circuit package system includes: forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the ...	09/20/2011
8017439	Dual carrier for joining IC die or wafers to TSV wafers A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first debonding temperature. The TSV wafer is thinned from a b...	09/13/2011

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Class 438/109 - Stacked array (e.g., rectifier, etc.)