Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 8178391 | Method for packaging semiconductors at wafer level A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming, in a first lithographically processable material disposed on the surface portion of the semiconductor waf... | 05/15/2012 |
| 8168470 | Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of fir... | 05/01/2012 |
| 8163599 | Flip-chip mounting method, flip-chip mounting apparatus and tool protection sheet used in flip-chip mounting apparatus A flip-chip mounting apparatus has a shield film (18) on the side of a pressurizing film (10b) of a tool protection sheet (10). When a semiconductor chip (1) is heated and pressurized via the tool protection sheet (10), the ... | 04/24/2012 |
| 8153473 | Module having a stacked passive element and method of forming the same A module having a discrete passive element and a semiconductor device, and method of forming the same. In one embodiment, the module includes a patterned leadframe, a discrete passive element mounted on an upper surface of the leadframe, and a thermally conductive, ... | 04/10/2012 |
| 8153474 | Modular low stress package technology A method of manufacturing a protected package assembly: providing a protective modular package cover in accordance with a modular design; selectively applying an adhesive to the cross member of each subassembly receiving section of the protective modular package cov... | 04/10/2012 |
| 8148201 | Planar interconnect structure for hybrid circuits Described herein is an electronic device in which one or more planar interconnect structure are interposed between two substrates each incorporating a hybrid circuit. The planar interconnect structure has a plurality of conductive traces formed on one of its faces f... | 04/03/2012 |
| 8143097 | Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP A semiconductor device is made by mounting a semiconductor wafer to a temporary carrier. A plurality of TSV is formed through the wafer. A cavity is formed partially through the wafer. A first semiconductor die is mounted to a second semiconductor die. The first and... | 03/27/2012 |
| 8143096 | Integrated circuit package system flip chip An integrated circuit package system includes: providing a substrate having a top side with a trace conductor connected to a bottom side with a system interconnect; forming a bump ring on the substrate, the bump ring having an inner cavity area over the trace conduc... | 03/27/2012 |
| 8138016 | Large area integration of quartz resonators with electronics Methods for integrating quartz-based resonators with electronics on a large area wafer through direct pick-and-place and flip-chip bonding or wafer-to-wafer bonding using handle wafers are described. The resulting combination of quartz-based resonators and large are... | 03/20/2012 |
| 8138017 | Integrated circuit package system with through semiconductor vias and method of manufacture thereof A method of manufacture of an integrated circuit package system includes: providing a package substrate; mounting a first integrated circuit die, having through silicon vias, on the package substrate; coupling cylindrical studs to the package substrate adjacent to t... | 03/20/2012 |
| 8133760 | System and method for backside circuit editing on full thickness silicon device A system for accessing circuitry on a flip chip circuit device with active circuitry and full-thickness bulk silicon includes a moveable surface for supporting and locating the circuit device in a plane, an infrared (IR) imaging device located at a defined perpendic... | 03/13/2012 |
| 8129220 | Method and system for bonding electrical devices using an electrically conductive adhesive A system for bonding electrical devices using an electrically conductive adhesive to adhere the electrical devices together, the system comprising: an ultrasonic transducer to generate an ultrasonic vibration; and an ultrasonic to thermal energy apparatus operativel... | 03/06/2012 |
| 8124449 | Device including a semiconductor chip and metal foils A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to th... | 02/28/2012 |
| 8124450 | Stacking multiple devices using single-piece interconnecting element An embodiment of the present invention is a technique to stack multiple devices using an interconnecting element. A board has a periphery and top and bottom surfaces. The top surface has top contact pads to attach to a first device. The bottom surface is milled down... | 02/28/2012 |
| 8119448 | Semiconductor chip, wafer stack package using the same, and methods of manufacturing the same A semiconductor chip comprises a substrate including a front surface and a rear surface, the substrate having a first via hole formed in the front surface and a second via hole formed in the rear surface, a first conductive plug formed on the substrate, the first co... | 02/21/2012 |
| 8114707 | Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip A temporary substrate having an array of first solder pads is bonded to the front side of a first substrate by reflowing an array of first solder balls. The first substrate is thinned by removing the back side, and an array of second solder pads is formed on the bac... | 02/14/2012 |
| 8110439 | Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector... | 02/07/2012 |
| 8105875 | Approach for bonding dies onto interposers A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. Af... | 01/31/2012 |
| 8105874 | Memory circuit arrangement and method for the production thereof A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that ... | 01/31/2012 |
| 8093100 | Integrated circuit packaging system having through silicon via with direct interconnects and method of manufacture thereof A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; ... | 01/10/2012 |
| 8093099 | Lock and key through-via method for wafer level 3D integration and structures produced A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination,... | 01/10/2012 |
| 8088645 | 3D smart power module A 3D smart power module for power control, such as a three phase power control module, includes a two sided printed circuit (PC) board with power semiconductor devices attached to one side and control semiconductor devices attached to the other side. The power semic... | 01/03/2012 |
| 8076179 | Fabrication method for integrated circuit chip component, multi-chip module, and their integration structure A multi-chip module and an integrated structure of the present invention including: at least one of either a terminal unit formation area expanded type integrated circuit chip, or a terminal unit formation area identical type integrated circuit chip; terminal unit f... | 12/13/2011 |
| 8076178 | Self-assembly of micro-structures Embodiments of a method for assembling a multi-chip module (MCM) are described. During this method, a fluid that includes coupling elements is applied to a surface of a base plate in the MCM. Then, at least some of the coupling elements are positioned into negative ... | 12/13/2011 |
| 8067267 | Microelectronic assemblies having very fine pitch stacking A method of making a stacked microelectronic assembly includes providing a first microelectronic package that includes a first substrate having a first dielectric layer, conductive posts, and conductive traces extending along the surface of the first dielectric laye... | 11/29/2011 |
| 8053276 | Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector... | 11/08/2011 |
| 8048715 | Multi-chip module and methods A substrate includes first and second regions over which first and second semiconductor devices are to be respectively positioned. The first region is located at least partially within the second region. Contact areas are located external to the first region but wit... | 11/01/2011 |
| 8043892 | Semiconductor die package and integrated circuit package and fabricating method thereof A semiconductor die package includes a substrate, a semiconductor die mounted on the substrates a molding covering the semiconductor die and which is formed on the substrate and a conductive layer laminated on the molding. ... | 10/25/2011 |
| 8039304 | Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structures A semiconductor device has dual-molded semiconductor die mounted to opposite sides of a build-up interconnect structure. A first semiconductor die is mounted to a temporary carrier. A first encapsulant is deposited over the first semiconductor die and temporary carr... | 10/18/2011 |
| 8039307 | Mounted body and method for manufacturing the same A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a)... | 10/18/2011 |
| 8039306 | 3D integration of vertical components in reconstituted substrates A reconstituted electronic device including: a first face and a second face; a plurality of individual chips placed perpendicular to the faces, each individual chip carrying, on one of its surfaces, at least one component, tracks, and a connection mechanism that are... | 10/18/2011 |
| 8039305 | Method for bonding semiconductor wafers and method for manufacturing semiconductor device In a method for bonding semiconductor wafers of the present invention, a bonding layer containing a flux-active curing agent and a thermosetting resin is interposed between a first semiconductor wafer and a second semiconductor wafer, thereby producing a semiconduct... | 10/18/2011 |
| 8039303 | Method of forming stress relief layer between die and interconnect structure A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the sem... | 10/18/2011 |
| 8039308 | Integrated-circuit package for proximity communication Embodiments of a multi-chip module (MCM) are described. This MCM includes a first semiconductor die and a second semiconductor die, where a given semiconductor die, which can be the first semiconductor die or the second semiconductor die, includes proximity connecto... | 10/18/2011 |
| 8034658 | Electronic module with a conductive-pattern layer and a method of manufacturing same This publication discloses an electronic module and a method for manufacturing an electronic module, in which a component (6) is glued (5) to the surface of a conductive layer, from which conductive layer conductive patterns (14) are later forme... | 10/11/2011 |
| 8030133 | Method of fabricating a bonded wafer substrate for use in MEMS structures A method of manufacturing a semiconductor device includes providing first and second semiconductor substrates, each having first and second main surfaces opposite to one another. A roughened surface is formed on at least one of the first main surface of the first se... | 10/04/2011 |
| 8030132 | Manufacturing method of semiconductor device including peeling step To simplify a peeling step in a method for manufacturing a semiconductor device including the peeling step. A first layer having a metal film is formed over a substrate; a second layer having a transistor is formed over the first layer having the metal film; a resin... | 10/04/2011 |
| 8026128 | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask A semiconductor device has a semiconductor die with an die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die over the substrate so that the bump ma... | 09/27/2011 |
| 8017436 | Thin substrate fabrication method and structure A method of forming a package includes forming a circuit pattern on a first carrier and embedding the circuit pattern in a dielectric material on a second carrier. The first carrier is removed and a buildup dielectric material is mounted to the dielectric material a... | 09/13/2011 |
| 8012796 | Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnec... | 09/06/2011 |
