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| Number | Title | Issue Date |
| 8187920 | Integrated circuit micro-module One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded ... | 05/29/2012 |
| 8183087 | Semiconductor device and method of forming a fan-out structure with integrated passive device and discrete component A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) is mounted to the temporary carrier using an adhesive. The IPD includes a capacitor and a resistor and has a plurality of thro... | 05/22/2012 |
| 8183088 | Semiconductor die package and method for making the same Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die. ... | 05/22/2012 |
| 8178390 | Semiconductor component and production method A semiconductor component is disclosed. In one embodiment, the semiconductor component includes a semiconductor chip, which is arranged on a substrate, and a housing, which at least partially surrounds the semiconductor chip. The substrate is at least partly provide... | 05/15/2012 |
| 8163598 | Clipless integrated heat spreader process and materials In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a... | 04/24/2012 |
| 8163596 | Stackable electronic package and method of making same An apparatus comprises a first chip layer comprising a first component coupled to a first side of a first flex layer, the first component comprising a plurality of electrical pads. The first chip layer also comprises a first plurality of feed-thru pads coupled to th... | 04/24/2012 |
| 8163597 | Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die... | 04/24/2012 |
| 8153472 | Embedded chip package process An embedded chip package process is disclosed. A first substrate having a first patterned circuit layer is provided. A second substrate having a second patterned circuit layer is provided. A dielectric material layer is formed to cover the first patterned circuit la... | 04/10/2012 |
| 8148198 | Method for reducing variations in the bending of rolled base plates and semiconductor module having such a base plate sensor A method for reducing variations in the bending of rolled metal base plates for semiconductor modules is disclosed. In this method, the base plates are rolled in their longitudinal direction in a specific manner. ... | 04/03/2012 |
| 8148199 | Method of electrically connecting a microelectronic component A microelectronic assembly is provided which can include an element including a first dielectric layer and a second dielectric layer overlying the first dielectric layer, the second dielectric layer having an exposed surface defining an exposed major surface of the ... | 04/03/2012 |
| 8148200 | Semiconductor device and manufacturing method of the same A wire short-circuit defect during molding is prevented. A semiconductor device has a tab, a plurality of leads arranged around the tab, a semiconductor chip mounted over the tab, a plurality of wires electrically connecting the electrode pads of the semiconductor c... | 04/03/2012 |
| 8143095 | Sequential fabrication of vertical conductive interconnects in capped chips A method is provided of forming a capped chip which includes a conductive interconnect exposed through an opening in the cap. A cap having openings extending between outer and inner surfaces is aligned and joined to a chip. A mass of fusible conductive material is p... | 03/27/2012 |
| 8138014 | Method of forming thin profile WLCSP with vertical interconnect over package footprint A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsu... | 03/20/2012 |
| 8138015 | Interconnection in multi-chip with interposers and bridges A structure formation method. The method may include: attaching a substrate, a first interposer, a second interposer, and a first bridge together such that the first interposer is on and electrically connected to the substrate, the second interposer is on and electr... | 03/20/2012 |
| 8133759 | Leadframe A leadframe includes a die paddle and leads, in which the back side of the die paddle has a fillister. The fillister defines a rim surrounding a recess, and the recess accommodates protrusion of fusible material. Also, a package includes such a leadframe. Also, a me... | 03/13/2012 |
| 8129219 | Semiconductor module, method for manufacturing the semiconductor module and portable device carrying the same In a semiconductor module where a metal sheet, an insulating layer and a circuit element are stacked in a manner that the insulating layer is penetrated with a bump structure, the connection reliability of the bump structure and the circuit element is enhanced. A se... | 03/06/2012 |
| 8124448 | Semiconductor chip with crack deflection structure Various die crack deflection structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating a semiconductor chip including an outer edge, a first side and a second side opposite to the first si... | 02/28/2012 |
| 8124446 | Structure of high performance combo chip and processing method A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by... | 02/28/2012 |
| 8124447 | Manufacturing method of advanced quad flat non-leaded package The manufacturing method of advanced quad flat non-leaded packages includes performing a pre-cutting process prior to the backside etching process for defining the contact terminals. The pre-cutting process ensures the isolation of individual contact terminals and i... | 02/28/2012 |
| 8119446 | Integrated chip package structure using metal substrate and method of manufacturing the same An integrated chip package structure and method of manufacturing the same is by adhering dies on a metal substrate and forming a thin-film circuit layer on top of the dies and the metal substrate. Wherein the thin-film circuit layer has an external circuitry, which ... | 02/21/2012 |
| 8119447 | Integrated circuit packaging system with through via die having pedestal and recess and method of manufacture thereof A method of manufacture of an integrated circuit packaging system includes: providing a structure having a via filled with conductive material completely through the structure, a recess, and a pedestal portion bordering the recess; mounting a semiconductor device in... | 02/21/2012 |
| 8114706 | Selective removal of gold from a lead frame A method of packaging an integrated circuit, including providing a lead frame having lead fingers, where the lead frame has a gold layer thereon on a top surface and a bottom surface. An integrated circuit die is attached to the lead frame. The gold layer is substan... | 02/14/2012 |
| 8110438 | Thermal method to control underfill flow in semiconductor devices A method and apparatus for assembling a semiconductor device. A chip (901) with solder bodies (903) on its contact pads is flipped onto a substrate (904). After the reflow process, a gap (910) spaces chip and substrate apart. A polymer pr... | 02/07/2012 |
| 8110437 | Method for attaching a semiconductor chip in a plastic encapsulant, optoelectronic semiconductor component and method for the production thereof A radiation-emitting or -receiving semiconductor chip 9 is soft-soldered for mounting on a leadframe 2 over which a prefabricated plastic encapsulant 5, a so-called premolded package, is injection-molded. Through the use of a low-melting solder ... | 02/07/2012 |
| 8105871 | Semiconductor device and manufacturing method of the same A semiconductor device includes a semiconductor element provided over a wiring board; sealing resin configured to seal the semiconductor element; and reinforcing resin provided at least at a part of a boundary part of the sealing resin and the wiring board. In the a... | 01/31/2012 |
| 8105873 | Flexible semiconductor device and identification label Provided is a flexible device (100) having an integrated circuit (5) and an antenna (6) which is incorporated or directly coupled to the interconnect structure of the integrated circuit (5). An electrically insulating or dielectric layer ... | 01/31/2012 |
| 8105872 | Semiconductor device and method of forming prefabricated EMI shielding frame with cavities containing penetrable material over semiconductor die A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable mat... | 01/31/2012 |
| 8101458 | Method of forming monolithic CMOS-MEMS hybrid integrated, packaged structures A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing a semiconductor substrate with pre-fabricated cmos circuits on the front side and a polished back-side with through substrate conductive vias; ... | 01/24/2012 |
| 8101457 | Mounting method, mounted structure, manufacturing method for electronic equipment, electronic equipment, manufacturing method for light-emitting diode display, and light-emitting diode display Provided is a mounting method making it possible to, when an object such as an element, or more particularly, a microscopic object is mounted on a substrate, achieve mounting readily and reliably with high positional precision by: forming an element holding layer | 01/24/2012 |
| 8097491 | Chip structure having redistribution layer and fabrication method thereof A chip structure having a redistribution layer includes: a chip with electrode pads disposed on an active surface thereof; a first passivation layer formed on the active surface and the electrode pads; a redistribution layer formed on the first passivation layer and... | 01/17/2012 |
| RE43112 | Stackable ball grid array package A stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top sur... | 01/17/2012 |
| 8097489 | Semiconductor device and method of mounting pre-fabricated shielding frame over semiconductor die A semiconductor device includes a pre-fabricated shielding frame mounted over a sacrificial substrate and semiconductor die. An encapsulant is deposited through an opening in the shielding frame around the semiconductor die. A first portion of the shielding frame to... | 01/17/2012 |
| 8097490 | Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is fo... | 01/17/2012 |
| 8084296 | Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One such device can include a first support member, a second support member, and a microelectronic die positioned between the first sup... | 12/27/2011 |
| 8084297 | Method of implementing a capacitor in an integrated circuit A method of implementing a capacitor in an integrated circuit package is disclosed. The method comprises coupling the capacitor to a first surface of a substrate of the integrated circuit package; positioning an integrated circuit die over the capacitor, wherein the... | 12/27/2011 |
| 8080442 | Vertical system integration The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes... | 12/20/2011 |
| 8080443 | Method of making pillars using photoresist spacer mask A method of making a device includes forming a first hard mask layer over an underlying layer, forming first features over the first hard mask layer, forming a first spacer layer over the first features, etching the first spacer layer to form a first spacer pattern ... | 12/20/2011 |
| 8080444 | Method for forming a packaged semiconductor device having a ground plane A method of placing a die includes providing an embedded plane. The embedded plane has a openings, grid lines, and protruding portions. Each of the plurality of openings are surrounding by a subset of the plurality of grid lines. At least one of the protruding porti... | 12/20/2011 |
| 8080445 | Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of... | 12/20/2011 |
| 8076177 | Scalable transfer-join bonding lock-and-key structures Scalable transfer-join bonding techniques are provided. In one aspect, a transfer-join bonding method is provided. The method includes the following steps. A first bonding structure is provided having at least one metal pad embedded in an insulator and at least one ... | 12/13/2011 |
