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...During the Civil War, the Confederacy established its own Patent Office which issued 266 patents, a third of which concerned implements of war.
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| Number | Title | Issue Date |
| 8110434 | Semiconductor device and memory card using the same A circuit board has a curved portion provided in at least one side of an external shape thereof. An external connecting terminal is provided on a first main surface of the circuit board. A semiconductor element is mounted on a second main surface of the circuit boar... | 02/07/2012 |
| 7816175 | Nano-elastic memory device and method of manufacturing the same A nano-elastic memory device and a method of manufacturing the same. The nano-elastic memory device may include a substrate, a plurality of lower electrodes arranged in parallel on the substrate, a support unit formed of an insulating material to a desired or predet... | 10/19/2010 |
| 7736943 | Carbon nanotube transistor fabrication During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A g... | 06/15/2010 |
| 7402456 | PCMO thin film with memory resistance properties A method is provided for forming a Pr0.3Ca0.7MnO3 (PCMO) thin film with crystalline structure-related memory resistance properties. The method comprises: forming a PCMO thin film with a first crystalline structure; and, changing the ... | 07/22/2008 |
| 7402736 | Method of fabricating a probe having a field effect transistor channel structure A probe of a scanning probe microscope having a sharp tip and an increased electric characteristic by fabricating a planar type of field effect transistor and manufacturing a conductive carbon nanotube on the planar type field effect transistor. To achieve this, the... | 07/22/2008 |
| 7349223 | Enhanced compliant probe card systems having improved planarity Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more ... | 03/25/2008 |
| 7332038 | Device for depositing in particular crystalline layers on one or more, in particular likewise crystalline substrates A device for depositing crystalline layers onto one or more substrates in a process chamber, including: a reverse-heatable support plate which forms a wall of the process chamber and which is heated with a high frequency and is formed of inertly coated graphite; a g... | 02/19/2008 |
| 7271047 | Test structure and method for measuring the resistance of line-end vias A test structure and methods of using and making the same are provided. In one aspect, a test structure is provided that includes a first conductor that has a first end and a second conductor that has a second end positioned above the first end. A third conductor is... | 09/18/2007 |
| 7259038 | Forming nonvolatile phase change memory cell having a reduced thermal contact area The invention provides for a nonvolatile memory cell comprising a heater layer in series with a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. Concentrating thermal energy in a relatively small volu... | 08/21/2007 |
| 7245068 | Apparatus for controlled alignment of catalytically grown nanostructures Systems and methods are described for controlled alignment of catalyticaly grown nanostructures in a large-scale synthesis process. An apparatus includes an electrode including: a protruding section defining an edge; and a nonprotruding section coupled to the protru... | 07/17/2007 |
| 7233030 | Device transfer method and panel A device transfer method includes the steps of: covering a plurality of devices, which have been formed on a substrate, with a resin layer; forming electrodes in the resin layer in such a manner that the electrodes are connected to the devices; cutting the resin lay... | 06/19/2007 |
| 7195950 | Forming a plurality of thin-film devices An aspect of the present invention is a method for forming a plurality of thin-film devices. The method includes coarsely patterning at least one thin-film material on a flexible substrate and forming a plurality of thin-film elements on the flexible substrate with ... | 03/27/2007 |
| 7174631 | Method of fabricating electrical connection terminal of embedded chip An electrical connection terminal of an embedded chip and a method for fabricating the same are disclosed. An insulating layer is provided on a circuit board integrated with a chip and has a plurality of first openings for exposing a conductive pad of the chip. A fi... | 02/13/2007 |
| 7176063 | High density 3-D integrated circuit package A slotted file is created by connecting two side walls and a back wall. The side walls have etched grooves facing directly across from each other. The platelet has flanges that fit into the grooves. In one embodiment, a completed cube is formed when the platelets fi... | 02/13/2007 |
| 7169684 | Device having inductors and capacitors and a fabrication method thereof An LC device having a substrate, a support layer having upper and lower sides formed on the substrate, inductors formed on either the upper or lower side of the support layer, and capacitors formed in the opposite side of the support layer. The support layer may be ... | 01/30/2007 |
| 7166490 | Semiconductor device with terminals, and method of manufacturing the same A plurality of semiconductor chips is mounted on a surface of a substrate to be used for manufacturing semiconductor devices. The semiconductor chips are collectively sealed with resin, thereby forming resin-sealed sections. A plurality of solder balls are formed on... | 01/23/2007 |
| 7165323 | Method of manufacturing a touch screen A method for manufacturing a touch screen that deposits a conductive layer or coating directly onto a surface of a sheet or ribbon or roll of thin glass material. The coated thin glass material may be cut to the desired shape or substrate for use as the outer, thin ... | 01/23/2007 |
| 7163848 | Semiconductor device and manufacturing method thereof OFF current of a TFT is reduced. There is provided a semiconductor device includung: a substrate; a shielding film formed so as to be in contact with the substrate; a planarization insulating film formed on the substrate so as to cover the shielding film; and a semi... | 01/16/2007 |
| 7147718 | Device and method for the deposition of, in particular, crystalline layers on, in particular, crystalline substrates The invention relates to a device and method for the deposition of in particular, crystalline layers on one or several, in particular, equally crystalline substrates in a process chamber, by means of reaction gases which are fed to the process chamber where they rea... | 12/12/2006 |
| 7148526 | Germanium MOSFET devices and methods for making same A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side.... | 12/12/2006 |
| 7115863 | Probe for scanning probe lithography and making method thereof A probe of scanning probe lithography which provides a long time of useful life. The probe has a tip part comprising a conductor and an insulator, the insulator is formed to cover the conductor, and the conductor is formed to provide a substantially uniform cross-se... | 10/03/2006 |
| 7023097 | FBGA arrangement The invention relates to an FBGA arrangement, comprising a substrate on which at least one chip is chip-bonded face-down, which has a central row of bonding pads connected to contact islands (landing pads) on the substrate by a bonding channel in the substrate via w... | 04/04/2006 |
| 7009412 | Massively parallel interface for electronic circuit Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated circuits (ICs) to test and burn-in equipment, for interconnecting modules... | 03/07/2006 |
| 7005363 | Method of forming a semi-insulating region A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask has a plurality of thicknesses and blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semic... | 02/28/2006 |
| 7002225 | Compliant component for supporting electrical interface component An apparatus in one example includes a compliant component for supporting an electrical interface component that serves to electrically and mechanically couple a die with a separate layer. In one example, the compliant component, upon relative movement between the d... | 02/21/2006 |
| 7002233 | Integrated circuit including an inductive element having a large quality factor and being highly compact An integrated circuit including a substrate, a conductive layer, at least one inductive element superposed on the conductive layer and formed by a metallic turn having an outer contour and an inner contour, which bound between them a surface referred to as the radia... | 02/21/2006 |
| 6958533 | High density 3-D integrated circuit package A slotted file is created by connecting two side walls and a back wall. The side walls have etched grooves facing directly across from each other. The platelet has flanges that fit into the grooves. In one embodiment, a completed cube is formed when the platelets fi... | 10/25/2005 |
| 6943055 | Method and apparatus for detecting backside contamination during fabrication of a semiconductor wafer A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant ... | 09/13/2005 |
| 6929983 | Method of forming a current controlling device A current-controlling device comprising a first conductor, a second conductor, and a tunneling barrier comprising a first insulating layer between the first conductor and the second conductor. The tunneling barrier electrically isolates the first conductor from the ... | 08/16/2005 |
| 6916682 | Semiconductor package device for use with multiple integrated circuits in a stacked configuration and method of formation and testing A package device (10, 100) has one integrated circuit (22, 122) in a cavity (20, 120) in a package substrate (12, 122) and electrically coupled to one side (50, 150) of the package substrate. A second integrated circuit (32, 132... | 07/12/2005 |
| 6855614 | Sidewalls as semiconductor etch stop and diffusion barrier Methods and apparatus of forming a semiconductor device using pedestals and sidewalls. The pedestals and sidewalls may provide an etch stop and/or a diffusion barrier during manufacture of a semiconductor device. Processes of forming diode connected vertical cylindr... | 02/15/2005 |
| 6803651 | Optoelectronic semiconductor package device An optoelectronic semiconductor package device includes a semiconductor chip, an insulative housing and a conductive trace, wherein the chip includes an upper surface and a lower surface, the upper surface includes a light sensitive cell and a conductive pad, the in... | 10/12/2004 |
| 6797528 | Micro probing tip made by micro machine method A method and apparatus for forming a micro tip for a micro probe utilized in testing semiconductor integrated circuit devices. A thick oxide layer is deposited upon a substrate initially to form the micro tip. The micro tip for the micro probe can be defined from th... | 09/28/2004 |
| 6706552 | Method for making interactive information devices with spacer elements An interactive information device for use as a touch panel, touch screen, digitizer panel, or pen-input device, and a method for making such a device includes a first, transparent, electrically conductive layer supported by the rigid substrate, a flexible, transpare... | 03/16/2004 |
| 6701614 | Method for making a build-up package of a semiconductor A method for making a build-up package of a semiconductor die and a structure formed from the same. A copper foil with conductive columns is bonded to an encapsulated die by thermal compression, between thereof there is a pre-curing dielectric film sandwi... | 03/09/2004 |
| 6610598 | Surface-mounted devices of light-emitting diodes with small lens The present invention is a surface-mounted device of light-emitting diodes (SMD LED) whose component typically has a plane on the surface. Through the calculation of Snell's Law, most of light fails to be emitted directly from the component because of the... | 08/26/2003 |
| 6586822 | Integrated core microelectronic package A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers... | 07/01/2003 |
| 6472712 | Semiconductor device with reduced transistor leakage current A semiconductor device improved to suppress a leakage current of a transistor is provided. A gate electrode is disposed on a semiconductor substrate. A pair of p type source/drain layers are provided on the surface of the semiconductor substrate, on both ... | 10/29/2002 |
| 6346432 | Semiconductor element having external connection terminals, method of manufacturing the semiconductor element, and semiconductor device equipped with the semiconductor element External connection terminals (25) are disposed on side surfaces, a back surface, or both the side surfaces and the back surface of a semiconductor element, especially an optical element (20) such as an image sensor, a solid state imaging device, etc. The... | 02/12/2002 |
| 6274402 | Method of fabricating a silicon solar cell A method of fabricating a back surface point contact silicon solar cell having p-doped regions and n-doped regions on the same side by forming a passivating layer on a surface of the cell having opened windows at the p-doped regions and the n-doped region... | 08/14/2001 |
