Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
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| Number | Title | Issue Date |
| 8189773 | Circuit updating system An information processing apparatus includes a reconfigurable unit in which a circuit is reconfigured. A generation unit generates design data for the circuit configured by the reconfigurable unit and reduces the amount of design data to be held by a design data sto... | 05/29/2012 |
| 8180046 | Method for making secure an electronic entity with encrypted access A method for protecting an electronic entity with encrypted access, against DFA (Differential Fault Analysis) attacks which includes: storing the result of a selected step (Rm, Kn) of an iterative process forming part of the cryptographic algorithm and in performing... | 05/15/2012 |
| 8175265 | Systems and methods for implementing block cipher algorithms on attacker-controlled systems Systems and methods for an implementation of block cipher algorithms (e.g., AES) use lookup tables to obscure key information, increasing difficulty for those with privileged access to a system performing the AES algorithm to obtain such key information. The impleme... | 05/08/2012 |
| 8155308 | Advanced encryption system hardware architecture A cryptographic device comprises a first pipeline stage, a pipeline register, and a second pipeline stage. The first pipeline stage comprises a first byte substitution module that performs mathematical operations on a received byte and outputs an intermediate value ... | 04/10/2012 |
| 8144865 | Protection of the execution of a DES algorithm A method for protecting an execution, by an integrated circuit, of a ciphering and/or deciphering algorithm taking into account data and at least one valid key and performing several iterations of the same calculation, including at least one execution of an iteratio... | 03/27/2012 |
| 8135130 | Data encryption apparatus, data converting method, data converting program, recording medium and integrated circuit The data encryption apparatus with a data converting unit splits 256-bit input data into 32-bit data blocks A1, B1, A2, and B2. A first combining unit performs an exclusive OR operation on A1 and B1, and on A2 and B | 03/13/2012 |
| 8121285 | Data processing for coding A system and method for data processing for coding. The method may include providing a first plurality of bytes of data, non-linearly transforming the first plurality of bytes into a second plurality of bytes, multiplying each of the second plurality of bytes of dat... | 02/21/2012 |
| 8121284 | Information processing system, information processing method, and information processing program To provide an architecture information processing system having a small circuit size capable of reducing power consumption and cost, on which system a circuit simultaneously executing encryption processing and message authentication (falsification detection processi... | 02/21/2012 |
| 8121286 | Hash function with provable resistance to differential attacks A system and method for coding data to help resist differential attacks. Data in m columns may be initialized to an initialized value. One new column of data may be mixed with a new input word and input to an advanced mixer. The advanced mixer may include linear mix... | 02/21/2012 |
| 8102997 | Processor for executing an AES-type algorithm A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comp... | 01/24/2012 |
| 8094816 | System and method for stream/block cipher with internal random states Disclosed herein are systems, methods, and computer readable-media for performing data encryption and decryption using a stream or block cipher with internal random states. The method includes splitting the input data into a predetermined number of blocks and proces... | 01/10/2012 |
| 8094815 | Arithmetic method and apparatus for supporting AES and ARIA encryption/decryption functions Provided are an arithmetic method and apparatus for supporting Advanced Encryption Standard (AES) and Academy, Research Institute and Agency (ARIA) encryption/decryption functions. The apparatus includes: a key scheduler for generating a round key using an input key... | 01/10/2012 |
| 8094814 | Method and apparatus for using counter-mode encryption to protect image data in frame buffer of a video compression system Certain aspects for protecting image data in a video compression system may include encrypting image data utilizing counter-mode scrambling. The encrypted image data may be buffered in at least one frame buffer. The buffered encrypted image data may be decrypted by ... | 01/10/2012 |
| 8085933 | Cipher for disk encryption Encryption is provided with additional diffusion components to construct a block cipher with a large and variable block size. The cipher incorporates an encryption system or algorithm such that the cipher is at least as secure as the encryption system or algorithm. ... | 12/27/2011 |
| 8073141 | Execution unit for performing the data encryption standard An execution unit adapted to perform at least a portion of the Data Encryption Standard. The execution unit includes a Left Half input; a Key input; and a Table input. The execution unit also includes a first group of transistors configured to receive the Table inpu... | 12/06/2011 |
| 8073140 | Encryption/decryption device, encryption/decryption method, and computer program It is possible to realize a Feistel-type common key block encryption/decryption processing configuration capable of reducing data stored in a memory at a low cost. The Feistel-type common key block encryption/decryption processing repeatedly executes an SP-type F fu... | 12/06/2011 |
| 8036379 | Cryptographic processing Executable instructions designed to provide faster cryptographic processing, fixed-timing memory access, and dedicated memory usage are implementable on an x86 CPU utilizing XMM registers. The instructions can be utilized to implement cryptographic processing in acc... | 10/11/2011 |
| 8014520 | Exponentiation ladder for cryptography Method and apparatus for data security using exponentiation. This is suitable for public key cryptography authentication and other data security applications using a one-way function. A type of exponentiation is disclosed here where the bits of an exponent value exp... | 09/06/2011 |
| 8000469 | Authentication engine architecture and method Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. Authentication engines in ... | 08/16/2011 |
| 7961875 | Means and method for ciphering and transmitting data in integrated networks The invention provides a method for ciphering and transmitting data, to be used by a communication device being arranged to transmit data through a first data port (241, 2002) according to a first transmission protocol, and to form ciphered exploiting a ciphe... | 06/14/2011 |
| 7949130 | Architecture and instruction set for implementing advanced encryption standard (AES) A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, tha... | 05/24/2011 |
| 7929690 | Two non-orthogonal states quantum cryptography method and apparatus with inter-and inter-qubit interference for eavesdropper detection An apparatus and method for implementing a secure quantum cryptography system using two non-orthogonal states. For each qubit, the to emitter station prepares a quantum system in one of two non-orthogonal quantum states in the time-basis to code bit values. Intra- a... | 04/19/2011 |
| 7903813 | Stream cipher encryption application accelerator and methods thereof A system for encrypting and decrypting data formed of a number of bytes using the ARCFOUR encryption algorithm is disclosed. The system includes a system bus and an encryption accelerator arranged to execute the encryption algorithm coupled to the system bus. A syst... | 03/08/2011 |
| 7831040 | DES hardware throughput for short operations A symmetric key cryptographic method is provided for short operations. The method includes batching a plurality of operation parameters (1503), and performing an operation according to a corresponding operation parameter (1505). The symmetric key crypt... | 11/09/2010 |
| 7809134 | Method for encrypting information and device for realization of the method The cryptographic system and method for securing data from unauthorized access includes, in one embodiment, an iterative probabilistic cipher for converting plaintext into ciphertext comprising at least two components, a core and a flag. A corresponding key and the ... | 10/05/2010 |
| 7801301 | Method and circuit for data encryption/decryption Data are converted between an unencrypted and an encrypted format according to the Rijndael algorithm, including a plurality of rounds. Each round is comprised of a fixed set of transformations applied to a two-dimensional array, designating states, of rows and colu... | 09/21/2010 |
| 7796750 | Method for making secure an electronic entity with encrypted access A method for protecting an electronic entity with encrypted access, against DFA (Differential Fault Analysis) attacks which includes: storing the result of a selected step (Rm, Kn) of an iterative process forming part of the cryptographic algor... | 09/14/2010 |
| 7787620 | Prevention of side channel attacks against block cipher implementations and other cryptographic systems Methods and apparatuses are disclosed for improving DES and other cryptographic protocols against external monitoring attacks by reducing the amount (and signal-to-noise ratio) of useful information leaked during processing. An improved DES implementation of the inv... | 08/31/2010 |
| 7778413 | Cryptographic system and method for encrypting input data A cryptographic system for encrypting input data in accordance with an encryption algorithm having a repeated-round structure may include an encryption unit updating and storing encrypted data in accordance with the encryption algorithm in each given round, and outp... | 08/17/2010 |
| 7747012 | Process of security of an electronic unit with cryptoprocessor The invention concerns a process for securing an electronic device incorporating a hardware component capable of autonomous implementation of calculation process f using one key K, the process involves calculating at least two new keys K′i such that at ... | 06/29/2010 |
| 7720220 | Cipher message assist instruction A method, system and program product for executing a cipher message assist instruction in a computer system by specifying, via the cipher message assist instruction, either a capability query installed function or execution of a selected function of one or more opti... | 05/18/2010 |
| 7715553 | Encrypting a plaintext message with authentication An encryption and authentication technique that achieves enhanced integrity verification through assured error-propagation using a multistage sequence of pseudorandom permutations. The present invention generates intermediate data-dependent cryptographic variables a... | 05/11/2010 |
| 7613295 | Cryptographic device and associated methods A cryptographic device includes an input stage receiving an input data block and a key data block made up of a plurality of sub-key data blocks, and generating a plurality of first signals therefrom. An intermediate stage is connected to the input stage and includes... | 11/03/2009 |
| 7606363 | System and method for context switching of a cryptographic engine A cryptographic system, method, and device for implementing cryptographic functions designed to protect data is provided. The method includes (a) providing an algorithm processing unit, (b) executing a cryptographic algorithm at the algorithm processing unit using a... | 10/20/2009 |
| 7606362 | FPGA configuration bitstream encryption using modified key Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment,... | 10/20/2009 |
| 7602906 | Cipher for disk encryption Encryption is provided with additional diffusion components to construct a block cipher with a large and variable block size. The cipher incorporates an encryption system or algorithm such that the cipher is at least as secure as the encryption system or algorithm. ... | 10/13/2009 |
| 7580519 | Triple DES gigabit/s performance using single DES engine Security processing circuits are discussed which may be used alone or as part of a network interface device of a host system using a single DES engine to accomplish 3DES processing. The security processing circuit is adapted for selectively encrypting outgoing data ... | 08/25/2009 |
| 7558386 | Countermeasure method in an electronic component using a secret key cryptographic algorithm In an electronic component using a secret key cryptographic algorithm, one operation utilizes a first table for supplying output data from input data. The output data, and/or derived data, is manipulated by critical instructions. A countermeasure method involves the... | 07/07/2009 |
| 7555121 | Methods and apparatus for implementing a cryptography engine Methods and apparatus are provided for implementing a cryptography engine for cryptography processing. A variety of techniques are described. A cryptography engine such as a DES engine running at a clock frequency higher than that of surrounding logic can be synchro... | 06/30/2009 |
| 7545928 | Triple DES critical timing path improvement Improved security processing circuits are discussed which may be used alone or as part of a network interface device of a host system using a DES engine to accomplish 3DES processing. The security processing circuit is adapted for selectively encrypting outgoing dat... | 06/09/2009 |
