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| Number | Title | Issue Date |
| 8000477 | Data security system and method for high bandwidth bus A data security system for a high bandwidth bus comprises a circular shift register operable to load a variable key value, and a scrambler coupled to the circular shift register operable to receive the variable key value from the circular shift register and serially... | 08/16/2011 |
| 7945049 | Stream cipher using multiplication over a finite field of even characteristic A first bit sequence is generated using a first pseudorandom bit source. A second bit sequence is generated using a second pseudorandom bit source. A third bit sequence is generated by multiplying the first bit sequence with the second bit sequence over a finite fie... | 05/17/2011 |
| 7860251 | Encryption-decryption circuit and method of operation An encryption-decryption circuit for encrypting and decrypting data. The encryption-decryption circuit comprises: 1) an N-bit shift register for storing and shifting an N bit keyword; 2) a first exclusive-OR gate array for receiving M bits from the N-bit shift regis... | 12/28/2010 |
| 7796759 | Diversification of a single integrated circuit identifier A method and a circuit of generation of several secret quantities by an integrated circuit according to the destination of these secret quantities, including taking into account a first digital word forming a single identifier of the integrated circuit chip and comi... | 09/14/2010 |
| 7747020 | Technique for implementing a security algorithm Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is pipelined within the processor architecture. ... | 06/29/2010 |
| 7724903 | Framing of transmit encoded data and linear feedback shifting Framing transmit encoded output data begins by determining a scrambling remainder between scrambling of an input code word in accordance with a 1st scrambling protocol and the scrambling of the input code word in accordance with an adjustable scrambling p... | 05/25/2010 |
| 7424116 | Method and apparatus for providing authentication in a communication system A method includes receiving an authentication request from a mobile station (401) and determining whether to forward the request to an authentication agent. When it is determined to forward the request, the request is forwarded to the authentication agent ( | 09/09/2008 |
| 7372965 | Electric circuit management method and device The invention proposes a method of managing an electronic circuit of the type comprising a memory (EEPROM) for the storage of confidential information, the method comprising masking variations of the electrical current (I) consumed by the electronic circuit, during ... | 05/13/2008 |
| 7369661 | Method and apparatus for detection of loss of cipher synchronization Detecting loss of stream cipher synchronization between a transmitter and a receiver in a video processing system may be achieved by receiving, by the receiver, an encrypted video frame from the transmitter, obtaining an encrypted value for a selected pixel in the ... | 05/06/2008 |
| 7366306 | Programmable logic device that supports secure and non-secure modes of decryption-key access Described are programmable logic devices that decrypt proprietary configuration data using on-chip decryption keys. The keys are stored in a key memory that can be operated in a secure mode or a non-secure mode. The non-secure mode allows the decryption keys to be r... | 04/29/2008 |
| 7334131 | Protected storage of a datum in an integrated circuit A method for protecting at least one first datum to be stored in an integrated circuit, including, upon storage of the first datum, performing a combination with at least one second physical datum coming from at least one network of physical parameters, and only sto... | 02/19/2008 |
| 7294935 | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misle... | 11/13/2007 |
| 7289558 | Infinite impulse response multiplierless digital filter architecture A multiplierless IIR filter incorporates power-of-two coefficients to perform shift operations to reduce space and increase speed. To optimize performance, a genetic algorithm generates the power-of-two coefficients. The filter architecture includes shift registers ... | 10/30/2007 |
| 7286666 | Countermeasure method in an electric component implementing an elliptical curve type public key cryptography algorithm A countermeasure method in an electronic component implementing an elliptical curve based public key cryptography algorithm. A new decryption integer d′ is calculated such that the decryption of an encrypted message on the basis of a private key d and the number o... | 10/23/2007 |
| 7277543 | Cryptographic combiner using two sequential non-associative operations A stream cipher cryptosystem includes a keystream generator receiving a key and providing a keystream. A cryptographic combiner combines a first binary data sequence and the keystream with two non-associative operations to provide a second binary data sequence. In e... | 10/02/2007 |
| 7263191 | Method and apparatus for encrypting data A method for encrypting data comprising dividing a first data set into a second data set and a third data set; deriving a first value using the second data set as an input into a polynomial equation; deriving a second value using the third data set as an input into ... | 08/28/2007 |
| 7248697 | Apparatus and method for scrambling and descrambling data wordwise in optical disk system An apparatus and a method for scrambling and descrambling data wordwise in an optical disk system are provided. The apparatus includes a bit storing means which stores at least 15 bits, and a calculating means which calculates first through fifteenth bits of the bit... | 07/24/2007 |
| 7248696 | Dynamic system bus encryption using improved differential transitional encoding The present invention provides data encryption for a differential bus employing transitional coding. The present invention maps, encodes and encrypts input data as a logic status for a given bus transfer cycle. The mapping, encoding and encrypting of the input data ... | 07/24/2007 |
| 7242063 | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when sta... | 07/10/2007 |
| 7217977 | Covert transformation of transistor properties as a circuit protection method A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are ap... | 05/15/2007 |
| 7219237 | Read- and write-access control circuits for decryption-key memories on programmable logic devices Described are various methods and systems for preventing unauthorized access to decryption keys on programmable logic devices. In one example, a key memory can operate in a secure mode or a non-secure mode. The non-secure mode allows decryption keys to be read or wr... | 05/15/2007 |
| 7218733 | Encryption method, program for encryption, memory medium for storing the program, and encryption apparatus, as well as decryption method and decryption apparatus The present invention relates to a cryptosystem. A keystream table [Ks] is a virtual data space. Every data of 1 byte in a secondary ciphertext E2 provides a vector directional component IR. The data Ks (IR) in the keystream table [Ks] designated by the d... | 05/15/2007 |
| 7203842 | Method and apparatus for secure configuration of a field programmable gate array A field programmable gate array (70) has security configuration features to prevent monitoring of the configuration data for the field programmable gate array. The configuration data is encrypted by a security circuit (64) of the field programmable gat... | 04/10/2007 |
| 7200235 | Error-checking and correcting decryption-key memory for programmable logic devices Described are circuits that detect and correct for decryption key errors. In one example, a programmable logic device includes a decryption key memory with a number of decryption-key fields and, for each key field, an associated error-correction-code (ECC) field. Th... | 04/03/2007 |
| 7197647 | Method of securing programmable logic configuration data The present invention relates to a secure method of distributing configuration data for a programmable logic device (PLD). The configuration data is encrypted to generate encrypted configuration data. A decryption key is encrypted using a silicon key. The encrypted ... | 03/27/2007 |
| 7194617 | Method and apparatus to prevent the unauthorized copying of digital information A method for authorizing the rendering of a digital recording. A first section and a last section of a track is first identified. A watermark is then decoded from the first and last sections of the track. It is then determined if at least one reserved bit is marked ... | 03/20/2007 |
| 7194088 | Method and system for a full-adder post processor for modulo arithmetic A full-adder post processor performs modulo arithmetic. The full-adder post processor is a hardware implementation able to calculate A mod N, (A+B) mod N and (A−B) mod N. The processor includes a full adder able to add the operands A and B while modulo reduction i... | 03/20/2007 |
| 7191340 | Generation of a secret quantity based on an identifier of an integrated circuit A method and a circuit for generating a secret quantity based on an identifier of an integrated circuit, in which a first digital word is generated from a physical parameter network, and this first word is submitted to at least one retroaction shift register, the ou... | 03/13/2007 |
| 7191339 | System and method for using a PLD identification code A method of programming a programmable logic device (PLD) includes identifying and reading an identification code on the PLD. At this point, a plurality of check bits can be generated based on the identification code. These check bits can be used to correct any erra... | 03/13/2007 |
| 7191333 | Method and apparatus for calculating a multiplicative inverse of an element of a prime field Techniques for implementing a digital signature algorithm in electronic computer hardware include computing the multiplicative inverse of a particular integer modulo a prime modulus by computing a first quantity modulo the prime modulus. The first quantity substanti... | 03/13/2007 |
| 7190787 | Stream cipher having a combiner function with storage based shuffle unit A stream cipher is provided with a first and a second data bit generators to generate in parallel a first and a second stream of data bits. The stream cipher is further provided with a combiner function having a shuffling unit including a storage structure to genera... | 03/13/2007 |
| 7177421 | Authentication engine architecture and method Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. Authentication engines in ... | 02/13/2007 |
| 7174014 | Method and system for performing permutations with bit permutation instructions The present invention provides permutation instructions usable in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. PPERM and PPERM3R instructions are defined to perform permutations by a sequence of... | 02/06/2007 |
| 7174016 | Modular exponentiation algorithm in an electronic component using a public key encryption algorithm The present invention concerns an anti-SPA modular exponentiation algorithm in an electronic component using a public key ciphering algorithm. A pair of registers and an indicator are used to provide symmetrical processing of bits in the algorithm, so that the value... | 02/06/2007 |
| 7171564 | Universal password generation method A method is provided for a user to generate a password for a software application accessible from a computer system which includes a universal password generator (UPG). The UPG includes a specified parameter for generating the password, and the software application ... | 01/30/2007 |
| 7166515 | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering A camouflaged interconnection for interconnecting two spaced-apart regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first region forming a conducting channel between th... | 01/23/2007 |
| 7162644 | Methods and circuits for protecting proprietary configuration data for programmable logic devices Described are various methods and systems for encrypting/decrypting configuration data for programmable logic devices. In configuration data defining a number of separately encrypted subdesigns, or “cores,” each subdesign includes a shared password or a unique a... | 01/09/2007 |
| 7159245 | Method for protecting a portable card A method for protecting a portable card, provided with at least a crypto algorithm for enciphering data and/or authenticating the card, against deriving the secret key through statistical analysis of its information leaking away to the outside world in the event of ... | 01/02/2007 |
| 7142675 | Sequence generator and method of generating a pseudo random sequence A sequence generator for generating a pseudo random sequence for random number generation or a stream cipher engine includes a plurality of linear feedback shift registers operable to generate a plurality of binary sequences. A plurality of nonlinear functions havin... | 11/28/2006 |
| 7134025 | Methods and circuits for preventing the overwriting of memory frames in programmable logic devices Described are various methods and systems for protecting proprietary configuration data for programmable logic devices. In one example, frames of configuration memory include overwrite-protect circuitry that reduces the risks associated with Trojan Horse attacks by ... | 11/07/2006 |
