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| Number | Title | Issue Date |
| 7961837 | Counter circuit and method of operating the same A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response ... | 06/14/2011 |
| 7609801 | Counter circuit and method of operating the same A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response ... | 10/27/2009 |
| 7359475 | Counter circuit and semiconductor device containing the same A counter circuit includes a counter section having flip-flops of a plurality of stages. The flip-flops from a first stage to an (N-1)th (N is an integer more than 2) stage synchronously count a clock signal. A mask circuit section controls supply of the ... | 04/15/2008 |
| 7292177 | Counter circuit, AD conversion method, AD converter, semiconductor device for detecting distribution of physical quantities, and electronic apparatus An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among three values, namely, non-in... | 11/06/2007 |
| 7276949 | Multiphase clock generation A first-phase clock signal is generated in response to a first input clock signal. A second-phase clock signal is generated one clock cycle of the first input clock signal after generating the first-phase clock signal in response to the first input clock signal. A t... | 10/02/2007 |
| 7272754 | Implementation-efficient multiple-counter value hardware performance counter An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based a... | 09/18/2007 |
| 7250740 | Method and apparatus for generating pulse-width modulated waveform In a method of generating pulse-width modulated waveform, the cycle of a carrier wave for the waveform is determined together with a first dead time value and a second dead time value both of which are set in a plurality of up-down counters, respectively. Using the ... | 07/31/2007 |
| 7234159 | Method and apparatus for controlling evaluation of protected intellectual property in hardware Various techniques permit more thorough development of digital systems and devices by designers while protecting the proprietary interests of the owners of the intellectual property incorporated in such systems and devices. More specifically, systems, apparatus, met... | 06/19/2007 |
| 7231012 | Programmable frequency divider A programmable frequency divider capable of operating in a normal mode and a fractional mode divides the input clock frequency by any integer ‘N’ provided at the input. In the normal mode the input is divided by the integer ‘N’. The divided output signal has... | 06/12/2007 |
| 7203265 | Synchronous counting circuit A M by N bit synchronous counter for use in advanced applications is provided. The M by N bit synchronous counter comprises an M by N register configured to receive and store data corresponding to at least one word integrated with a N bit counter configured to seque... | 04/10/2007 |
| 7196558 | Frequency divider with slip An apparatus has a frequency divider accepting a clock. The frequency divider is selectable between an N divide factor and an M divide factor via a divide mode signal, where an absolute value of (N−M)=1. The apparatus also has a pulse generator responsive to a sli... | 03/27/2007 |
| 7142543 | High speed programmable counter A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the... | 11/28/2006 |
| 7092479 | Ripple counter circuits in integrated circuit devices having fast terminal count capability and methods of operating the same Ripple counter circuits in integrated circuit devices can have fast terminal count capability. A terminal count circuit can be configured to mask selected unstable counter bits generated by a ripple counter circuit using an indication that a terminal state of the ri... | 08/15/2006 |
| 7064617 | Method and apparatus for temperature compensation Temperature compensation is achieved by adjusting a divide ratio of a multi-modulus divider circuit in a feedback path of a phase-locked loop based on the detected temperature. The divide ratio is adjusted based on stored adjustment values stored in non-volatile mem... | 06/20/2006 |
| 7057941 | Three-state memory cell A memory cell with at least two detectable states among which is an unprogrammed state, comprising, in series between two terminals of application of a read voltage, at least one first branch comprising: a pre-read stage comprising, in parallel, two switchable resis... | 06/06/2006 |
| 7049987 | Arrangement for generating a clock signal for a sigma-delta analog-to-digital converter In a method for generating a scanning clock signal (S) for scanning an analog signal (Ua) for an analog-to-digital converter (20) operating according to the sigma-delta method, a variable period (T; T*) of the power supply system (PL) is ascertained in time u... | 05/23/2006 |
| 7042257 | Frequency divider with reduced jitter and transmitter based thereon An apparatus for generating an output signal whose frequency is lower than the frequency of an input signal is disclosed. The apparatus includes a chain of frequency dividing cells where each cell has a definable division ratio. Furthermore, the frequency dividing c... | 05/09/2006 |
| 7030674 | Multiphase clock generators Multiphase clock generators and methods are provided. A multiphase clock generator has a first clock divider for generating a first-phase clock signal from a first input clock signal. A first logic gate is connected to an output port of the first clock divider. A se... | 04/18/2006 |
| 7005837 | Digital potentiometer including output buffer A digital potentiometer is disclosed that includes first, second, and third signal terminals. A chain of series-connected impedance elements with multiple tap points is connected between the first and second signal terminals. A plurality of first switching devices a... | 02/28/2006 |
| 6976157 | Circuits, systems and methods for performing branch predictions by selectively accessing bimodal and fetch-based history tables Branch prediction circuitry including a bimodal branch history table, a fetch-based branch history table and a selector table is provided. The local branch history table includes a plurality of entries each for storing a prediction value and accessed by selected bit... | 12/13/2005 |
| 6961403 | Programmable frequency divider with symmetrical output A programmable frequency divider circuit with symmetrical output is disclosed. The frequency divider includes a non-symmetrical LFSR based component operated in series with a symmetrical divider component. Both the LFSR and the symmetrical divider may be programmed ... | 11/01/2005 |
| 6952121 | Prescaling for dividing fast pulsed signal Circuits, devices and methods are provided for dividing a fast pulse signal by an integer M. A dual modulus prescaler receives input pulses, counts them, and generates one prescaled pulse for every Qth input pulse. Q is a division modulus, and has a different value ... | 10/04/2005 |
| 6950958 | Method and apparatus for dividing a high-frequency clock signal and further dividing the divided high-frequency clock signal in accordance with a data input A method including frequency dividing a high-frequency clock signal into a divided frequency, and further dividing the divided frequency into another divided frequency in accordance with a data input (DIN). ... | 09/27/2005 |
| 6882699 | Monotonic up-counter in an integrated circuit An increasing monotonic counter over n bits formed as an integrated circuit, including an assembly of 2n+1−(n+2) irreversible counting cells distributed in at least n groups of 2p−1 counting cells, where p designates the group rank, and at ... | 04/19/2005 |
| 6795000 | Programmable converter having an automatic channel sequencing mode A counter circuit is provided which is particularly suitable for controlling cyclical events. The counter consists of a chain of logic elements 160, 167, 164 which sequentially pass a ‘1’ along the chain in response to a clock signal. Each element is also... | 09/21/2004 |
| 6784929 | Universal two dimensional (frame and line) timing generator A programmable two-dimensional timing generator according to the invention employs a clock generator (102) and a user-defined two-stage waveform generator (106, 108). A single static random access memory (SRAM) (112) stores a user-defined wavefo... | 08/31/2004 |
| 6731176 | Synthesizer with lock detector, lock algorithm, extended range VCO, and a simplified dual modulus divider The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit imp... | 05/04/2004 |
| 6690525 | High-speed programmable synchronous counter for use in a phase locked loop A high-speed programmable synchronous counter is disclosed. The high speed counter includes a most-significant-bit counter synchronized with a least-significant bit counter. The least-significant-bit counter is programmed to an initial state and configure... | 02/10/2004 |
| 6566918 | Divide-by-N clock divider circuit with minimal additional delay A divide-by-N clock divider circuit adds little additional delay on the clock path. N can be any integer, and the value of N does not affect the clock path delay. The divide-by-N clock divider circuits of the invention include a control circuit and a logi... | 05/20/2003 |
| 6501816 | Fully programmable multimodulus prescaler The present invention is a method and system for a fully programmable modulus pre-scaler. In one embodiment, the pre-scaler is a cascade of fully programmable divide-by-2/3 sections. A fully programmable divide-by-2/3 section includes a state machine and ... | 12/31/2002 |
| 6329855 | Frequency synthesizer A frequency synthesizer has a voltage controlled oscillator to generate a oscillation signal of a frequency corresponding to a control voltage, a divider to divide the oscillation signal and to generate a dividing signal, a reference signal oscillator to ... | 12/11/2001 |
| 6320927 | Electronic counter It is an object of the present invention to make it possible to optionally configure various types of electronic counters. Therefore, the present invention is provided with a one-chip microcomputer 12 having a built-in ROM 13 and RAM 14 to write data corr... | 11/20/2001 |
| 6314524 | Repetitive interval timing An interval timer for timing multiple repetitive timing intervals. A single large clock register increments ticks of a high-speed clock. Successive previously-stored timing values are loaded into a single compare register which is preferably of equivalent... | 11/06/2001 |
| 6263450 | Programmable and resettable multifunction processor timer The programmable timer for use in a microprocessor has a counter and a reset register each connected to a databus of the microprocessor, and a first comparator for comparing the counter against the reset register in providing the result of the comparison ... | 07/17/2001 |
| 6157695 | Counter for performing multiple counts and method thereof A loadable counter circuit which is able to perform multiple contiguous counts. The loadable counter circuit uses a counter for monitoring a number of specified events. A data storage device is coupled to the counter for loading the counter with counter v... | 12/05/2000 |
| 6133796 | Programmable divider circuit with a tri-state inverter A programmable dividing circuit comprises a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages being configured so that when an output of the last stage is supplied to a f... | 10/17/2000 |
| 6114915 | Programmable wide-range frequency synthesizer Method and circuitry for a frequency synthesizer having wide operating frequency range. The frequency synthesizer uses multiple programmable loadable counters in a phase-locked loop arrangement to generate any combination of clock frequencies based on use... | 09/05/2000 |
| 6094100 | PLL synthesizer apparatus Disclosed herein is a fractional N-type PLL frequency synthesizer apparatus. A fractional N-type control circuit employed therein for varying N values for each reference cycle is constructed of a combination of a frequency divider (comprising D flip-flops... | 07/25/2000 |
| 6072338 | Method of and device for determining pulse width A pulse width determining device includes a down counter for counting down from a first initial count value reloaded thereinto. If the down counter underflows, it can start counting down from a second initial count value reloaded thereinto as needed. Ever... | 06/06/2000 |
| 6072849 | Shift counter device A programmable n stage shift counter divider circuit includes a plurality of n flip-flops arranged in cascade from a first stage to an nth stage. The data inputs of each of the flip flops are coupled with the output of the next preceding stage through cor... | 06/06/2000 |
