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| Number | Title | Issue Date |
| 7345515 | Low power and low timing jitter phase-lock loop and method A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. Th... | 03/18/2008 |
| 7343510 | Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals A clock detection and selection circuit (100) can include a first counter (102-0) that generates a first count value CNT1 according to a first clock signal CLK1 and a second counter (102-1) that generates a second cou... | 03/11/2008 |
| 7343387 | Algorithm for configuring clocking system A system and method for configuring an automatic test system to produce a plurality of clocks from a reference clock includes a user interface and software. The user interface receives a plurality of inputs that specify desired frequencies of the plurality of clocks... | 03/11/2008 |
| 7342986 | Digital PLL device A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring ... | 03/11/2008 |
| 7343255 | Dual source real time clock synchronization system and method A dual source real time clock (RTC) synchronization system and method for implementation within automatic meter reading (AMR) systems that provide system-wide device time synchronization. In one embodiment, a microcontroller-implemented RTC counts elapsed seconds fr... | 03/11/2008 |
| 7342980 | Estimating carrier phase in communication systems Disclosed herein are methods, articles, and apparatus for estimating a carrier phase in a communication system. A method, according to one aspect, may include receiving carrier phase estimation information, and estimating a carrier phase based on the carrier phase e... | 03/11/2008 |
| 7342426 | PLL with controlled VCO bias In some embodiments, a PLL with an output to provide a PLL output clock at a target frequency is provided. The PLL comprises a VCO to generate a clock to be used to generate the PLL output clock. Also provided is circuitry to maintain the VCO's bias level at a suffi... | 03/11/2008 |
| 7342521 | System and method for multi-channel delay cell based clock and data recovery Systems and methods regarding the restoration of serialized data to parallel data with a low speed reference signal are provided. In exemplary embodiments, a phased lock loop receives a reference clock signal from a data source and generates a reference high speed c... | 03/11/2008 |
| 7342985 | Delay locked loop with fixed angle de-skew, quick start and low jitter Digital delay locked loops which generate fixed angle delayed (e.g., quadrature) clock signals based on a reference clock signal and that accounts for clock signal delay. The number of quadrature delay elements is calculated based on the number of delay elements nee... | 03/11/2008 |
| 7342953 | Synchronization detection circuit A synchronization detection circuit includes: a matched filter 105 for outputting a correlation value, between a spreading code and data that is obtained by sampling a code spread signal 101, using a sampling clock for one chip cycle; a sampling clock ... | 03/11/2008 |
| 7342982 | Demodulation apparatus for a network transceiver and method thereof A transceiver of a communication system is disclosed. The transceiver is implemented by a demodulation apparatus including a front-end receiver, a noise canceller, a feedforward equalizer (FFE) and a decoding system. The front-end receiver receives a remote signal a... | 03/11/2008 |
| 7340220 | Phase locked loop with power distribution A phase locked loop includes a detection module, a control conversion module, a controlled oscillation module, a divider module, and a power distribution module. The detection module is operably coupled to produce a difference signal based on a difference between a ... | 03/04/2008 |
| 7340233 | Integrated circuit and methods for third sub harmonic up conversion and down conversion of signals An integrated circuit may include a receiver and/or a transmitter that performs third order sub-harmonic conversion. The integrated circuit may include a Gilbert cell active mixer with three or more serially-connected transistors in each of the mixer's four branches... | 03/04/2008 |
| 7340655 | Skew adjustment circuit, skew adjustment method, data synchronization circuit, and data synchronization method A skew adjustment circuit employs a novel algorithm enabling a reduction in scale of the circuit of a receiver for a Transition Minimized Differential Signaling (T.M.D.S.) link in accordance with the Digital Visual Interface (DVI) standard. The skew adjustment circu... | 03/04/2008 |
| 7340633 | Method for automatically detecting the clock frequency of a system clock pulse for the configuration of a peripheral device The present invention provides a method for automatic identification of the clock frequency of a system clock (15) for the configuration of a peripheral device (12), having the following steps: generation of a secondary clock (16) at a predeterm... | 03/04/2008 |
| 7339412 | Digital clock generator The invention relates to a clock generator comprised of a system clock input (2) for applying a high-frequency system clock signal, of a digital input (3) for applying a settable digital increment value, of an adder (6) for adding the increment ... | 03/04/2008 |
| 7340266 | Method and apparatus for communicating with multimode receiving device in non-synchronized wireless systems An apparatus, such as a network element (112), for use in a system that communicates with a multimode receiving device (110), employs an information gating buffer (400) that is operably coupled to a first wireless system transmitter (404)... | 03/04/2008 |
| 7339420 | Method of switching PLL characteristics and PLL circuit A loop filter which is a component of a PLL circuit includes a switching element for switching a capacitance value which connects and disconnects a second capacitive element to a first capacitive element according to a natural angular frequency switching signal, and... | 03/04/2008 |
| 7340021 | Dynamic phase alignment and clock recovery circuitry A dynamic phase alignment circuit is provided that aligns data signals to a phase of a forwarded clock at each channel in a multi-channel communications protocol. A forwarded clock is sent to a phase locked loop (PLL) circuit that generates multiple clock phases of ... | 03/04/2008 |
| 7336755 | PLL with low phase noise non-integer divider A phase-locked loop with a non-integer divider utilizes a state machine to periodically select a new clock from a plurality of clocks for comparison to a reference signal after division by an integer divide by N block. Based on a desired divider ratio, the state mac... | 02/26/2008 |
| 7336752 | Wide frequency range delay locked loop A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and... | 02/26/2008 |
| 7336702 | Jitter detecting apparatus and phase locked loop using the detected jitter A jitter detecting circuit and a phase locked loop using the detected jitter are provided. A jitter detecting circuit detecting a jitter value of a signal which is converted into a digital signal from an analog signal input, wherein the jitter value detecting circui... | 02/26/2008 |
| 7336723 | Systems and methods for high-efficiency transmission of information through narrowband channels Systems and methods for transmitting information at very high data rates through narrowband communication channels are provided. The systems and methods involve modulating a message signal with a novel return-to-zero, abrupt phase modulation technique and filtering ... | 02/26/2008 |
| 7337356 | Systematic and random error detection and recovery within processing stages of an integrated circuit An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture e... | 02/26/2008 |
| 7336753 | Transmitter Briefly, a transmitter that includes first and second fractional N synthesizers that may generate outphased modulated signals. First and second sigma-delta modulators may control the modulation of the first and second fractional N synthesizers. ... | 02/26/2008 |
| 7336748 | DDS circuit with arbitrary frequency control clock A test system using direct digital synthesis for generation of a spectrally pure, agile clock. The clock is used in analog and digital instruments in automatic test system. A DDS circuit is synchronized to the tester system clock because it is clocked by a DDS clock... | 02/26/2008 |
| 7336110 | Differential amplitude controlled sawtooth generator A dual differential sawtooth signal generator includes a first sawtooth voltage generator that has a first capacitor and a second capacitor that are alternately charged with a feedback control source current from a low voltage reference voltage level. A second sawto... | 02/26/2008 |
| 7336934 | Transmission modulation apparatus Linear transmission modulation apparatus 100 has high frequency amplifier 102 that amplifies the high frequency phase modulation signal of a high frequency signal and power source voltage controller 101 that amplifies the baseband amplitude modu... | 02/26/2008 |
| 7337216 | Electronic system architecture An electronic system architecture comprises a plurality of client devices connected in a hierarchical structure in which the client devices form nodes in the structure interconnected by communications links. One client device at the top of the hierarchical structure... | 02/26/2008 |
| 7336111 | Fast-locking digital phase locked loop An apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is... | 02/26/2008 |
| 7336754 | Clock and data recovery circuit A clock and data recovery circuit, for tracking frequency-modulated input data, comprises a phase detector for receiving a data signal and a synchronous clock signal, detecting a phase delay or a phase advance, and outputting an UP1/DOWN1 signal, first... | 02/26/2008 |
| 7336106 | Phase detector and method having hysteresis characteristics A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a seco... | 02/26/2008 |
| 7333209 | Fiber optic gyroscope asynchronous demodulation A clock system for a fiber optic gyroscope is provided that includes a highly-tunable clock for the bias modulation and a separate asynchronous high-speed clock for the photodetector sampling. By separating the two clocks rather than using two derivatives of the sam... | 02/19/2008 |
| 7333423 | Transceiver with calibrated I and Q paths and methods for deconvolved calibration Phase and amplitude offsets of a multicarrier transceiver may be reduced by measuring receiver amplitude and phase mismatches of receiver radio-frequency (RF) circuitry by performing a fast Fourier transform (FFT) on a receiver calibration signal. ... | 02/19/2008 |
| 7334153 | Low-speed DLL employing a digital phase interpolator based upon a high-speed clock A low-speed delay locked loop (DLL) facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference d... | 02/19/2008 |
| 7333468 | Digital phase locked loops for packet stream rate matching and restamping A packet stream multiplexer may include one or more control loops (e.g., digital phase locked loops) for tracking the source clock frequency associated with a packet stream. A first control loop may slowly drive an error between a received timestamp and an estimated... | 02/19/2008 |
| 7333780 | Polar modulation transmission apparatus and radio communication apparatus A polar modulation transmission apparatus is provided which can adjust synchronization between an amplitude signal and phase signal in a simple configuration accurately and automatically. A polar signal generation circuit 101 sends an amplitude signal and pha... | 02/19/2008 |
| 7332950 | DLL measure initialization circuit for high frequency operation A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the shift register. The reset circuitry selectively filters a clock signal propagation through the measured d... | 02/19/2008 |
| 7333578 | Linear data recovery phase detector An input data sequence is sampled according to a sampling clock such that a first set of samples corresponds to data values and a second set of samples corresponds to edges between the data values. The phase error between data transitions in the input sequence and t... | 02/19/2008 |
| 7333527 | EMI reduction using tunable delay lines The clock signal is the dominant source of electromagnetic interference (EMI) for many digital electronic devices. EMI generated by these electronic devices must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. The pr... | 02/19/2008 |
