Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 7400690 | Adaptive phase controller, method of controlling a phase and transmitter employing the same The present invention is directed to an adaptive phase controller employing a threshold level and a method of controlling a phase. In one embodiment, the adaptive phase controller includes a comparator configured to receive a comparison signal representing a phase a... | 07/15/2008 |
| 7397883 | Spread spectrum type clock generation circuit for improving frequency modulation efficiency The present invention provides a spread spectrum type clock generation circuit whose EMI for peripheral equipment is reduced. The clock generation circuit comprises a phase-locked loop circuit and a clock modulation circuit. The clock modulation circuit comprises a ... | 07/08/2008 |
| 7397882 | Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase compar... | 07/08/2008 |
| 7397881 | Erroneous phase lock detection circuit The present invention is concerned with a phase comparator circuit and provides an erroneous phase lock detection circuit that detects erroneous phase lock occurring when the duty cycle of data deviates from 100% in a comparison of a phase difference between the dat... | 07/08/2008 |
| 7397847 | Testing device for testing electronic device and testing method thereof A testing device for testing an electronic device is provided. The testing device includes: a deterministic jitter application unit for applying deterministic jitter to a given input signal without causing an amplitude modulation component and supplying the input si... | 07/08/2008 |
| 7397880 | Synchronization circuit and synchronization method In a synchronization circuit and a synchronization method, a first variable delay circuit generates a first pulse to be synchronized with a reference pulse, a second pulse which is leading in the phase to the first pulse, and a third pulse which is delayed in the ph... | 07/08/2008 |
| 7394320 | Phase-locked loop and method for operating a phase-locked-loop A phase-locked loop suitable for mobile radio communications and a method for operating the same is disclosed. One embodiment of the phase-locked loop comprises an oscillator, a counter, a comparator, and a delay arrangement. The counter comprises a first input conn... | 07/01/2008 |
| 7394418 | Apparatus comprising a sigma-delta modulator and method of generating a quantized signal-delta modulator A method of generating a quantized signal in a Sigma-Delta modulator (25) comprises the steps of feeding a modulator input signal to a quantizer (15) via at least one integrator (12, 13); generating in the quantizer (15) a quantized signa... | 07/01/2008 |
| 7394884 | Synchronizing method To synchronize a regularly occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the phase shifted signals is selected as an output signal. The output sign... | 07/01/2008 |
| 7394885 | Spread-spectrum clock signal generator A spread-spectrum clock signal generator includes a circuit loop receiving a reference signal at a reference frequency and adapted to generate an output signal at an output frequency dependent on and locked to the reference frequency, and a modulator circuit generat... | 07/01/2008 |
| 7391839 | Accumulator based phase locked loop There is disclosed a phase locked loop comprising: a phase frequency detector for receiving as a first input a reference signal and for generating a control signal; a voltage controlled oscillator for receiving the control signal and for generating a signal defining... | 06/24/2008 |
| 7391838 | Transceiver system and method supporting multiple selectable voltage controlled oscillators A phase lock loop comprising a plurality of voltage controlled oscillators is presented herein. The phase lock loop can provide a wide range of output frequencies with low jitter. Additionally, the phase lock loop can be incorporated into a clock multiplier unit and... | 06/24/2008 |
| 7391840 | Phase locked loop circuit, electronic device including a phase locked loop circuit and method for generating a periodic signal A phase locked loop (PLL) circuit (1) comprising a loop input (11); a phase detector section (2) for detecting a phase difference between an input signal and a reference signal. The phase detector section (2) has a detector input connected to th... | 06/24/2008 |
| 7391842 | Direct synthesis clock generation circuits and methods Clock signal generation circuitry includes input circuitry for receiving a frequency control input signal and a clock signal and generating a memory address therefrom, a memory for storing digital data indexed by the memory address and representing real and imaginar... | 06/24/2008 |
| 7391841 | Frequency synthesizer A plurality of voltage controlled oscillators and a plurality of dividers are provided corresponding to a plurality of frequency bands, respectively, and a phase comparator, a charge pump, and a low pass filter are used in common for the plurality of frequency bands... | 06/24/2008 |
| 7388939 | Fractional-R frequency synthesizer A fractional-R synthesizer having a divider with rational increments and configurable in rational steps able to generate a plurality of frequencies in rational increments from a reference frequency. A voltage-controlled oscillator frequency (fVCO) is rela... | 06/17/2008 |
| 7386085 | Method and apparatus for high speed signal recovery A closed-loop circuitry includes, in part, a loop filter and a current source/sink coupled to the loop filter to adjust the phase/frequency of the signal generated by the closed-loop circuitry. Because the voltage generated by the loop filter has a relatively low fr... | 06/10/2008 |
| 7385539 | All-digital phase locked loop (ADPLL) system An all-digital phase locked loop system for generating an oscillator output signal under control of a digital reference input. The system comprises a digitally controlled oscillator, a digital loop filter for generating a multiple bit digital control signal for the ... | 06/10/2008 |
| 7382849 | Charge pump circuit Charge pump circuit. A charge pump circuit is provided for use in a phase-lock loop circuit. The charge pump circuit comprises a charge pump core circuit that outputs a control voltage. The charge pump circuit also comprises a replica circuit that is coupled to the ... | 06/03/2008 |
| 7379521 | Delay circuit with timing adjustment function In a phase locked loop circuit, a phase comparator compares the phase of input clock and that of output clock, and provides a control signal as the comparison result. A charge pump circuit includes a clamp circuit, and based on the control signal, provides a control... | 05/27/2008 |
| 7375591 | Robust false locking prevention in referenceless frequency acquisition An output of an oscillator of a phase-locked loop is swept across a predetermined frequency range by varying control settings associated with the oscillator. A plurality of control settings that cause the oscillator to lock or falsely lock to the timing of an input ... | 05/20/2008 |
| 7372311 | Delay locked loop for controlling duty rate of clock There is provided a DLL capable of controlling a duty rate of a clock by a fuse option or an EMRS input. The DLL includes a first clock buffer, a second clock buffer, a first delay line, a second delay line, a shift register, a first duty control unit, a second duty... | 05/13/2008 |
| 7372932 | Locking-status judging circuit for digital PLL circuit A locking-status judging circuit is composed of a comparator that compares a phase error signal with a reference signal for judging whether or not a digital PLL circuit locks on an input signal and outputs a signal “0 (zero)” or a signal “1 (one)”, a selecto... | 05/13/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7372339 | Phase lock loop indicator A phase-locked loop (PLL) circuit includes a power-on-reset (POR) to reset a digital block and set an initial input voltage value VCTRL of voltage-controlled oscillator (VCO). An input divider and a feedback divider are provided to set the frequency ratio of output ... | 05/13/2008 |
| 7372928 | Method and system of cycle slip framing in a deserializer A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit s... | 05/13/2008 |
| 7372340 | Precision frequency and phase synthesis with fewer voltage-controlled oscillator stages A clock synthesis circuit) including a phase-locked loop and one or more frequency synthesis circuits is disclosed. The phase-locked loop includes a voltage-controlled oscillator (VCO) having a sequence differential stages o produce equally spaced clock phases. The ... | 05/13/2008 |
| 7368962 | Clock supply device Each clock supply unit comprises an inter-unit synchronization portion which operates when the clock supply unit is acting as a standby unit, using a clock signal from a DPLL of a unit which is active as reference, to apply a predetermined phase difference to the ou... | 05/06/2008 |
| 7369578 | Digital processing of SONET pointers In a method of estimating a bit rate (f1) of a digital signal conveyed through a SONET network between an originating node and a terminating node, the digital signal received by the originating node is processed to determine a result of a first function of th... | 05/06/2008 |
| 7369600 | Burst communications apparatus and method using tapped delay lines A communications apparatus and method use tapped delay lines as multiplexers and demultiplexers. In one embodiment, a receiver (100) uses a tapped delay line (110) as a demultiplexer to acquire a burst communication at very high data rates in the range... | 05/06/2008 |
| 7368966 | Clock generator and clock duty cycle correction method A clock duty cycle correction (DCC) circuit for correcting a clock duty cycle of an external clock includes a phase comparator for comparing a phase of a rising clock with that of a falling clock to thereby output comparing signal; a DCC controller for outputting a ... | 05/06/2008 |
| 7366267 | Clock data recovery with double edge clocking based phase detector and serializer/deserializer A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholl... | 04/29/2008 |
| 7366271 | Clock and data recovery device coping with variable data rates A clock and data recovery (CDR) device is disclosed that is capable of recovering a clock signal from a data signal that has a variable data rate. The CDR device includes a reference clock generating section for dividing a basic clock by a first predetermined value ... | 04/29/2008 |
| 7366244 | Method and system for antenna interference cancellation A wireless communication system can comprise two or more antennas that interfere with one another via free space coupling, surface wave crosstalk, dielectric leakage, or other interference effect. The interference effect can produce an interference signal on one of ... | 04/29/2008 |
| 7365797 | Display synchronization signal generation apparatus in digital broadcast receiver and decoder A display synchronization signal generation apparatus and method is provided which makes it possible to display a stable image irrespective of changes in transmission speed of a received digital broadcast signal by generating a synchronization signal of an image to ... | 04/29/2008 |
| 7366275 | Output calibrator with dynamic precision An integrated circuit device having an output driver circuit and a control circuit. The output driver circuit outputs a first signal having a signal level according to a control value. The control circuit is coupled to receive the first signal from the output driver... | 04/29/2008 |
| 7366269 | False lock detection circuit and false lock detection method, PLL circuit and clock data recovery method, communication device and communication method, and optical disk reproducing device and optical disk reproducing method Disclosed herein is a false lock detection circuit including: a data signal input section receiving an input of a data signal; a clock signal input section receiving an input of a clock signal generated from the data signal; a pattern detector obtaining the data sig... | 04/29/2008 |
| 7365609 | Hybrid stochastic gradient based digitally controlled oscillator gain Kestimation A novel hybrid stochastic gradient adaptation apparatus and method for calibrating the gain of an RF or non-RF digitally controlled oscillator (DCO). The adaptation algorithm determines a true stochastic gradient between a forcing function and its corresponding syst... | 04/29/2008 |
| 7366270 | PLL/DLL dual loop data synchronization utilizing a granular FIFO fill level indicator A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. In particular, a system and method for dual loop data synchronization using a granular FIFO fill level indicator is provided. A dual loop data serializer includes a ... | 04/29/2008 |
| 7365607 | Low-power, low-jitter, fractional-N all-digital phase-locked loop (PLL) A method for synthesizing frequencies with a low-jitter an all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, wherein the electronic circuit comprises a digital phase-frequency detector (DPFD) opera... | 04/29/2008 |
