Famous Patents
British merchant Peter Durand invented the tin can in 1810.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7317777 | Digital adaptive control loop for data deserialization A system and method for tracking/adapting phase or frequency changes in an incoming serial data stream that may contain significant amounts of noise and/or jitter and may contain relatively long periods of successive univalue data bits. The method includes digitally... | 01/08/2008 |
| 7317778 | Phase-locked loop control circuit An electrical circuit is disclosed, which comprises a phase locked loop (PLL) circuit and a PLL start-up circuit configured to selectively provide a reference signal to the phase locked loop circuit based upon relative frequencies of an input signal to the phase loc... | 01/08/2008 |
| 7317359 | Circuits and methods for phase locked loop lock window detection Circuits and methods for detecting the lock status of a phase locked loop (PLL). The circuit generally comprises (a) a controller configured to produce a control signal in response to a reference clock signal, (b) a counter configured to count pulses of an output si... | 01/08/2008 |
| 7315732 | Method for frequency conversion and receiver A method and device for frequency conversion is disclosed in which a first signal with a first frequency is converted into a second frequency through mixing with a divided oscillator signal and wherein the frequency of the divided oscillator signal stands in a fract... | 01/01/2008 |
| 7315602 | Digital spread spectrum frequency synthesizer The present invention provides a digital spread spectrum frequency synthesizer that comprises a noise-shaped quantizer, a divider and an adjustment means. The noise-shaped quantizer is used to quantize a period control word to a time-varying value. The divider is us... | 01/01/2008 |
| 7315599 | Skew correction circuit A skew correction circuit includes a first circuit and a second circuit. The first circuit generates at least one pulse train signal in response to a data bit signal and a first strobe signal. A duty cycle of the pulse train signal is indicative of a degree of skew ... | 01/01/2008 |
| 7315213 | Semiconductor device and voltage-controlled oscillation circuit A voltage-controlled oscillation circuit (15) includes a plurality of independent ring oscillation circuits different in the number of stages; and a selector (22) selectively outputting as a feedback clock signal (FB) an output of one of the ring oscil... | 01/01/2008 |
| 7315596 | Interpolator based clock and data recovery (CDR) circuit with digitally programmable BW and tracking capability The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit (300,700) at mul... | 01/01/2008 |
| 7315215 | Direct digital synthesizer with variable reference for improved spurious performance Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locke... | 01/01/2008 |
| 7315216 | Adjusting frequency device of built-in oscillator for USB interface and method thereof An adjusting frequency device of built-in oscillator for USB interface and a method thereof are described. It is Auto detect the error of bit-rate between the USB host and the USB device, and produce tiny counting time for clocking the clock error between the USB ho... | 01/01/2008 |
| 7315601 | Low-noise sigma-delta frequency synthesizer A sample-and-hold (SAH) phase detector (PD) is clocked in such a way (using a reverse clocking mode) so as to avoid quantization noise increases due to folding that is generally associated with conventional charge pump based phase detectors. The PD is clocked with a... | 01/01/2008 |
| 7313178 | Transceiver for receiving and transmitting data over a network and method for testing the same The present invention provides a transceiver for receiving and transmitting data over a network, and a method for testing the same. In particular, the present invention provides a physical layer transceiver having a built-in-self-test (BIST) device that allows for, ... | 12/25/2007 |
| 7312642 | Continuous, wide-range frequency synthesis and phase tracking methods and apparatus Circuitry and methods are provided for continuously adjustable frequency synthesis. The synthesis covers a wide range of possible frequencies and can be performed to a high degree of precision. In an embodiment of the invention, an analog phase-locked loop (“PLLâ€... | 12/25/2007 |
| 7312645 | Adaptive transition density data triggered PLL (phase locked loop) Adaptive transition density data triggered PLL (Phase Locked Loop). A novel solution is presented within a data triggered PLL whereby the missing data edge transitions may be detected and used to modify a phase difference between a data signal and a feedback signal ... | 12/25/2007 |
| 7312663 | Phase-locked loop having a bandwidth related to its input frequency An integrated circuit includes a phase-locked loop (PLL) in which the loop bandwidth of the PLL is proportional to the input frequency of the PLL. The PLL includes a phase/frequency detector (PFD), a charge pump, a loop filter, and a voltage-controlled oscillator (V... | 12/25/2007 |
| 7312666 | PLL circuit configured to distribute its loop control signal to CDR circuits A semiconductor integrated circuit includes a phase-locked loop (PLL) circuit configured to generate an oscillation output signal synchronized with a reference clock and a plurality of clock and data recovery (CDR) circuits configured to adjust a phase of the oscill... | 12/25/2007 |
| 7312667 | Statically controlled clock source generator for VCDL clock phase trimming The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock sour... | 12/25/2007 |
| 7310401 | Programmable frequency detector for use with a phase-locked loop A frequency detector for use with a PLL utilizes a counter and a preset value to produce frequency information related to a VCO signal. The frequency information is used to control the frequency of the VCO signal and to determine whether the VCO signal should be con... | 12/18/2007 |
| 7310011 | Clock signal adjuster circuit The present invention relates to a clock signal distribution circuit for distributing the clock signal to circuits such as LSI integrated circuits, and, more specifically, provides a clock adjuster circuit, which performs phase difference adjustment of clock signals... | 12/18/2007 |
| 7310397 | Data recovery circuit, phase detection circuit and method for detecting and correcting phase conditions In the data recovery circuit of the invention, a first group of sampling clock pulses is used for sampling approximately the central portions of the data bits in an incoming data stream to produce a first sampled data stream, while a second group of sampling clock p... | 12/18/2007 |
| 7310021 | Phase-locked loop with tunable-transfer function Embodiments of a phase-locked loop having a tunable-transfer function are presented herein. In implementations, a multipulse generator coupled between the chase frequency detector and charge pump tunes the bandwidth and peaking of the phase-locked loop based on an a... | 12/18/2007 |
| 7310365 | Group decision rule in code tracking using a delay lock loop (DLL) System and method for code acquisition in a wireless communications system with a delay lock loop. A preferred embodiment comprises assigning a delay lock loop (DLL) to each path in a received signal with multipath, adjusting each DLL to maximize sample strength, gr... | 12/18/2007 |
| 7310389 | Method and apparatus for determining the errors of a multi-valued data signal that are outside the limits of an eye mask Disclosed herein is a method and apparatus used to measure the number of time a multi-valued data signal transmitted from either a communication device of subsystem deviates across and into one or more bounded areas or zones as defined by an eye mask that is overlai... | 12/18/2007 |
| 7310400 | Data recovery device and method A data recovery device. The device adjusts a digital signal according to a pulse signal output by a phase-locked loop circuit. The sampling circuit samples each bit of the digital signal five times to generate a first sampled signal. The data delay buffer decides a ... | 12/18/2007 |
| 7308066 | Clock recovery circuit capable of automatically adjusting frequency range of VCO A clock recovery circuit capable of automatically adjusting the frequency range of a VCO (Voltage controlled Oscillator) without involving a look-up-table. The clock recovery circuit includes a main PLL (Phase locked loop) and an auxiliary PLL. The main PLL is a typ... | 12/11/2007 |
| 7308062 | Apparatus for providing system clock synchronized to a network universally Provided is an apparatus for providing a system clock synchronized to a network universally. The apparatus includes a network synchronization reference signal generating unit that outputs a reference signal for network synchronization; a network synchronization cont... | 12/11/2007 |
| 7308060 | Self correcting data re-timing circuit and method An eye opener circuit is provided which performs a data re-timing/eye opening function on a data signal after having been corrupted by jitter. The circuit uses a PLL driven by a clock source which was the same clock source used in timing the data signal originally. ... | 12/11/2007 |
| 7308048 | System and method for selecting optimal data transition types for clock and data recovery A clock recovery circuit samples an incoming data stream that includes sequences of signal transitions. A transition detector categorizes the received signal transitions into various types, such as those associated with 2PAM and 4PAM signaling schemes. Select logic ... | 12/11/2007 |
| 7304545 | High latency timing circuit A phase locked loop (PLL) circuit, comprises a frequency integrator circuit that receives a target signal, a phase shift signal and a frequency gain correction parameter and that selectively disables tracking frequency offset based on a value of the frequency gain c... | 12/04/2007 |
| 7305020 | Method and system of reducing electromagnetic interference emissions A method and system is disclosed for spreading the power associated with digital signals being transmitted to lower electromagnetic interference (EMI) emissions. After being transmitted across a transmission line, a representation of the original digital signal is r... | 12/04/2007 |
| 7305060 | Spread range control apparatus A spread range control apparatus of the present invention controls a clock generator, which generates a spread spectrum clock based on setting of spread data, so as to regulate a spread range of the spread spectrum clock. The spread range control apparatus includes:... | 12/04/2007 |
| 7304516 | Method and apparatus for digital phase generation for high frequency clock applications An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal. The first phase signal is delayed by the phase alignment magnitude to generate a first phase delay signal.... | 12/04/2007 |
| 7304510 | Digital phase detector improving phase detection resolution thereof A digital phase detector has a plurality of first delay elements through which a first clock is delayed, a plurality of second delay elements through which a second clock is delayed, and a plurality of data holding circuits. The data holding circuits latch the first... | 12/04/2007 |
| 7301831 | Memory systems with variable delays for write data signals Systems and methods for generating write data signals having variable delays for use in write operations to memory components are provided. These memory systems and methods include receiving a write data signal and a corresponding data valid or timing signal (also r... | 11/27/2007 |
| 7301997 | Method and apparatus for improved high-speed adaptive equalization A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred em... | 11/27/2007 |
| 7298809 | Self-calibration of a PLL with multiphase clocks A Phase-Locked Loop with multiphase clocks is provided. The Phase-Locked Loop includes a main loop, a calibration loop, and a Demultiplexer. The main loop includes, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Multi-Phase ... | 11/20/2007 |
| 7299022 | Carrier detecting circuit and infrared communication device using same A carrier detecting circuit which generates a carrier detection level by integral action based on a reception signal and detects using the carrier detection level whether a carrier exists is disclosed and includes an integration capacitor that is charged and dischar... | 11/20/2007 |
| 7298220 | Method and apparatus for creating a multiple loop VCO Disclosed herein is a method and apparatus used to create an idealized voltage controlled oscillator (VCO) which allows very high modulation rates without the expected phase noise (jitter) which nominally comes from wide bandwidth VCOs. In this fashion, high quality... | 11/20/2007 |
| 7295049 | Method and circuit for rapid alignment of signals Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of ... | 11/13/2007 |
| 7295643 | Method and a device for phase and frequency comparison The phase and frequency comparator for controlling, as a function of the frequency (Fref) and the phase of a reference signal (Sref), the frequency (Fvco) and the phase of the output signal of a controlled-frequency oscillator compri... | 11/13/2007 |
