Class 375/376 - Phase locked loop

Subclass of Class 375 - Pulse or digital communications
Definition: Subject matter having a closed-loop electronic servomechanism
No. of patents: 3098
Last issue date: 05/29/2012

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Number	Title	Issue Date
8189730	Method and apparatus for system time clock recovery Briefly, a system time clock (STC) recovery apparatus includes an STC counter that receives a program clock reference (PCR) signal. The STC recovery apparatus also includes a phase lock loop that generates an STC signal having an STC frequency and a fractional divid...	05/29/2012
8184762	Digital phase lock loop with multi-phase master clock A digital phase lock loop circuit provides an output with reduced jitter. The digital phase lock loop circuit includes a phase frequency detector that determines a phase difference between a feedback signal and a reference frequency signal to generate an error signa...	05/22/2012
8184761	Controlling phase locked loop A method and apparatus for controlling phase locked loop are provided. The apparatus includes a voltage controlled oscillator configured to generate an output signal with a frequency proportional to a control voltage fed into the oscillator. The apparatus also inclu...	05/22/2012
8170171	Communication semiconductor integrated circuit A communication semiconductor integrated circuit, has: a first computing element which adds the count value and the phase difference value and outputs a first computed value as an addition result; a second computing element which adds set frequency data obtained by ...	05/01/2012
8165258	Clock generating device and method thereof A clock generating device includes: a frequency divider having an input node coupled to a transmission interface for generating a reference clock signal according to an input data received from the transmission interface; and a clock/data recovery circuit having a d...	04/24/2012
8165260	Loop bandwidth enhancement technique for a digital PLL and a HF divider that enables this technique A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first and a second plurality of cycles and receiving a feedback signal (512) having the firs...	04/24/2012
8165259	Method and device for processing the frequency shift of the carrier frequency of a signal modulated with a quadrature continuous single-carrier modulation A frequency shift of a carrier frequency of an input signal is estimated with a frequency estimator in order to obtain an estimate value. Then, the estimate of the frequency shift is refined, and the carrier frequency is corrected in consequence, with a phase-locked...	04/24/2012
8160196	Networking methods and systems A network system includes integrated radio transceivers and digitizers, integrated baseband processors and device controllers, digital interfaces there between, and architectures and partitions for same. Licensing methodologies are provided for implementing the feat...	04/17/2012
8155257	Synchronizing circuit and controlling method thereof Disclosed herein is synchronizing circuit including: a numerically controlled oscillating section; a phase rotating section; a phase error estimating section; a loop filter; and a gain controlling section; wherein the gain controlling section controls the gain so as...	04/10/2012
8139704	Phase compensated renormalizable dynamic phase locked loop A variable bandwidth phase locked loop (PLL) includes renormalizable circuitry configured to allow a gain of the PLL to be changed without causing a disturbance, and a phase compensation circuit configured to adjust a final output phase of the PLL based on parameter...	03/20/2012
8139703	Data relay apparatus and semiconductor integrated circuit having the same A data relay apparatus according to one embodiment described herein can include a phase detection unit that can detect a phase difference between a clock output from a transmitter and a clock output from a receiver, and generate a plurality of phase detection signal...	03/20/2012
8135105	Circuit for correcting an output clock frequency in a receiving device An output clock correction circuit (14) for correcting a frequency of an output clock in a receiving device (13) that receives data (16) and a time stamp component (18) includes an output clock feedback loop (20), a FIFO buffer (	03/13/2012
8130892	ADPLL frequency synthesizer In an ADPLL frequency synthesizer where a frequency control word is changed from FCW0 to FCW2, a control sensitivity estimation section firstly measures oscillatory frequencies f1L and f1H obtained, respectively, whe...	03/06/2012
8121242	Frequency lock stability in device using overlapping VCO bands A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO is selected. Using a phase-locked loop (PLL) and the initial VCO, th...	02/21/2012
8111800	Frequency ratio detection A system and method are provided for determining a frequency ratio in a phase-locked loop (PLL) circuit feedback path. The method accepts a reference signal having a predetermined first frequency and a PLL output signal having a non-predetermined second frequency. T...	02/07/2012
8111799	Method, system and apparatus for reducing power consumption at low to midrange resolution settings A method for reducing power consumption in an information handling system (IHS) where the method includes receiving main data through a main link, wherein the main link provides at least one data lane. The IHS also receives a reference clock corresponding to the mai...	02/07/2012
8107581	Method for frequency compensation in timing recovery A method of digitally controlling a timing recovery loop to control jitter and reduce word-length in a recovered clock is provided. A timing error detector provides an output identifying the error sign. First and second randomizing digital attenuators provide first ...	01/31/2012
8107582	Methods and apparatus for digital clock recovery A method and apparatus for clock recovery in synchronous digital systems. The apparatus includes a phase frequency detector, a loop filter, a compressor, and a clock generator. The phase frequency detector generates a phase error signal based on a difference between...	01/31/2012
8098788	System and method for automatic leakage control circuit for clock/data recovery and charge-pump phase locked loops An apparatus that includes a module for controlling the frequency of a voltage controlled oscillator (VCO) as part of a phase locked loop (PLL), or clock and data recovery (CDR) when an input reference signal to the PLL or serial data to the CDR has ceased from bein...	01/17/2012
8098787	Method and apparatus for precision quantization of temporal spacing between two events One or two Serializer/Deserializer (SerDes) modules are used to measure the time between two pulses with high resolution. A PLL inside a SerDes block is locked to a reference clock and an input signal is passed through a storage element to create a serial data strea...	01/17/2012
8094770	Dynamic phase tracking using edge detection that employs an edge counter A phase-locked loop includes a sample selector configured to select a set of samples from an oversampled portion of a data signal, a dynamic phase decision control circuit configured to indicate whether a predetermined number of edges is present in the set of sample...	01/10/2012
8094769	Phase-locked loop system with a phase-error spreading circuit A phase-locked loop (PLL) system including a phase-frequency detector for generating an up signal or a down signal based on a phase difference between a reference clock and a feedback clock is provided. The PLL system further includes a phase-error spreading circuit...	01/10/2012
8090069	Apparatus for generating clock signal with jitter and test apparatus including the same The present invention relates to an apparatus for generating a clock signal with jitter and a test apparatus including the same. The apparatus for generating a clock signal with jitter in accordance with the present invention includes a voltage-controlled crystal os...	01/03/2012
8090070	Synchronizing device for USB real-time audio data transmission The present invention discloses a synchronizing device for real-time USB audio data transmission, comprising: a first adder unit, a start-of-frame countdown unit, a phase-locked loop circuit, a frequency divider, a second adder unit, a third adder unit, a fourth add...	01/03/2012
8090068	System and method of calibrating power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL) A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating th...	01/03/2012
8085893	Low jitter clock recovery circuit A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjus...	12/27/2011
8077822	System and method of controlling power consumption in a digital phase locked loop (DPLL) An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering ...	12/13/2011
8064562	Digital frequency locked delay line A device includes a signal generator having a delay locked circuit for providing a number of output signals based on an input signal. The output signals have a fixed signal relationship with each other and with the input signal. The signal generator also includes a ...	11/22/2011
8059777	Method and apparatus for generating phase shifted local oscillator signals for a feedback loop on a transmitter A transmitter is provided with a local oscillator (LO) processing unit to maintain stability in the transmitter's feedback loop. The LO processing unit includes at least one delay locked loop (DLL) and a programmable divider to generate phase shifted LO signals for ...	11/15/2011
8059778	Automatic clock frequency acquisition A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecti...	11/15/2011
8054931	Systems and methods for improved timing recovery Various embodiments of the present invention provide systems and methods for improved timing recovery. As one example, some embodiments of the present invention provide timing recovery circuits that include an error signal and a digital phase lock loop circuit. The ...	11/08/2011
8054930	Clock recovery circuit A circuit is provided for clock recovery. The circuit includes a reference extraction unit for extracting from a datastream time references defining a reference time base, and a digital Phase Locked Loop including a first programmable counter in the guise of a digit...	11/08/2011
8050376	All digital phase-locked loop with widely locked frequency An all-digital phase-locked loop (ADPLL) composed of digital circuits is provided. The ADPLL includes a phase-frequency detector (PFD), a control unit, a digital controlled oscillator (DCO), and a plurality of frequency dividers. A first frequency divider divides a ...	11/01/2011
8045670	Interpolative all-digital phase locked loop An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF ...	10/25/2011
8045669	Digital phase-locked loop operating based on fractional input and output phases In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference bet...	10/25/2011
8040995	Jitter detection circuit and jitter detection method A jitter detection circuit includes an oscillation circuit, a measurement period setting circuit for outputting a measurement period signal based on a measurement period specifying signal, the measurement period setting circuit receiving the output clock from a PLL ...	10/18/2011
8040994	Phase coefficient generation for PLL A method and apparatus is provided for synchronizing a clock signal by generating time varying PLL phase coefficients which approximate optimal PLL phase coefficients. An acquisition mode phase coefficient is determined by adding an error signal (A) to the sample co...	10/18/2011
8040996	Method and system for RF signal generation utilizing a synchronous multi-modulus divider Aspects of a method and system for RF signal generation utilizing a synchronous multi-modulus divider are provided. In this regard, a feedback signal of a PLL may be generated by clocking a counter with an RF signal output by the PLL and toggling the feedback signal...	10/18/2011
8036334	Delay lock loop phase glitch error filter A method and apparatus is provided for providing a phase glitch error filter for a delay lock loop. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal. The delay lock loop...	10/11/2011
8027423	Synchronizing apparatus, synchronizing method, synchronizing program and data reproduction apparatus A synchronizing apparatus, which controls, by a PLL circuit, a sampling clock to be used to sample input data and synchronizes a phase of the sampling clock with a target phase that is desirable for sampling the input data, includes: phase error detection means for ...	09/27/2011

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Class 375/376 - Phase locked loop