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"That the automobile has practically reached the limit of its development is suggested by the fact that during the past year no improvements of a radical nature have been introduced."
Scientific American ; Jan. 2 edition, 1909
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| Number | Title | Issue Date |
| 7050450 | Telecommunications system and method for producing a master clock in the same A telecommunications system includes devices to provide output clock signals that are synchronous to at least one source clock signal. A main clock generator includes a selector to select one of the output clock signals. The main clock generator generates a main clo... | 05/23/2006 |
| 7049896 | High latency timing circuit A phase locked loop circuit includes a frequency integrator responsive to a received signal. A phase integrator is responsive to the frequency integrator and a phase shift measurement circuit is responsive to the phase integrator and in communication with the freque... | 05/23/2006 |
| 7046718 | Coherent phase synchronous code division multiple access communications from multiple transponder platforms A method for coherent phase synchronous CDMA communications between a gateway and multiple subscribers via multiple transponder platforms that includes the step of synchronizing a local reference clock for each subscriber in a service area to a single master referen... | 05/16/2006 |
| 7042970 | Phase frequency detector with adjustable offset A phase detection apparatus is described for use in a phase lock loop (PLL). The apparatus has a first input for a reference signal, a second input for a loop feedback signal and an output for the phase difference signal. Two D-type flips flops are provided, the fir... | 05/09/2006 |
| 7043392 | Interpolator testing system According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs... | 05/09/2006 |
| 7039146 | Method and interface for glitch-free clock switching A clock switching technique allows selecting an input clock signal from two clock sources. The two clock sources are asynchronous to one another and a clock select signal is used to determine which of the clocks will be switched onto the clock output line. The clock... | 05/02/2006 |
| 7038496 | Device for comparison of frequencies with low temporal inertia The present invention relates to a device for comparison CMP, which is designed to emit a control signal Vcnt, which is representative of a difference which exists between the input signal frequencies Vdiv and Vref. The device according to the invention includes a p... | 05/02/2006 |
| 7039147 | Delay locked loop circuitry for clock delay adjustment Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phas... | 05/02/2006 |
| 7038497 | Differential current mode phase/frequency detector circuit A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be... | 05/02/2006 |
| 7039144 | Large-input-delay variation tolerant (LIDVT) receiver adopting FIFO mechanism The present invention discloses a multiple-stage FIFO mechanism capable of receiving data signals correctly. The circuit includes a write-enable pulse sequencer for sequentially generating a plurality of write-enable signals. An N-stage FIFO sequentially stores an i... | 05/02/2006 |
| 7034723 | Timing comparator, data sampling apparatus, and testing apparatus A data sampling apparatus includes plural stages of first variable delay elements for sequentially delaying a data signal by a first delay amount, plural stages of second variable delay elements for sequentially delaying a strobe signal by a second delay amount whic... | 04/25/2006 |
| 7035367 | Fractional multi-modulus prescaler A fractional multi-modulus prescaler is disclosed wherein the output of the VCO is separated into four signals 90 degrees phase-related to one another. The phase signals are selected by a multiplexer for application of a division function during the modulus time per... | 04/25/2006 |
| 7034597 | Dynamic phase alignment of a clock and data signal using an adjustable clock delay line A dynamic phase adjustment circuit that includes a multi-tap delay line that receives a clock input signal. The multi-tap delay line includes an initial portion that is adjustable, and final portion after the adjustable portion. A number of registers receive the sam... | 04/25/2006 |
| 7034596 | Adaptive input logic for phase adjustments Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently ... | 04/25/2006 |
| 7030674 | Multiphase clock generators Multiphase clock generators and methods are provided. A multiphase clock generator has a first clock divider for generating a first-phase clock signal from a first input clock signal. A first logic gate is connected to an output port of the first clock divider. A se... | 04/18/2006 |
| 7031420 | System and method for adaptively deskewing parallel data signals relative to a clock A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality... | 04/18/2006 |
| 7031858 | Method and circuit for DC measurement of phase uniformity of multi-phase clocks Methods and circuits for measuring clock phase uniformity of multi-phase clock set, including by generating at least one DC phase difference signal such that the DC phase difference signal is, or the DC phase difference signals are, indicative of the phase differenc... | 04/18/2006 |
| 7028205 | Techniques to monitor transition density of an input signal Techniques to determine and indicate the extent to which transitions of an input signal deviate from a desired transition region. In an implementation, an indication may be provided when a transition of an input signal occurs within the desired transition region and... | 04/11/2006 |
| 7024171 | Fractional-N frequency synthesizer with cascaded sigma-delta converters Frequency synthesizer utilizing fractional-N synthesis includes a phase detector having an input receivable of a reference frequency, a loop filter arranged to receive the signal from the phase detector, a tunable oscillator arranged to receive a tuning signal gener... | 04/04/2006 |
| 7023943 | Detector for detecting timing in a data flow A detector detects timing in a digital data flow with a bit-time equal to T. A first circuit generates four local timing signals each having periods substantially equal to the bit-time. Each of the four local timing signals are out of phase with one another by ΒΌ pe... | 04/04/2006 |
| 7023944 | Method and circuit for glitch-free changing of clocks having different phases A circuit for glitch-free changing of clocks having different phases. The circuit comprises a phase detector for receiving a data stream and a system clock, and generating a phase-up signal and a phase-down signal; a flag signal generator for receiving the phase-up ... | 04/04/2006 |
| 7023868 | Voice gateway with downstream voice synchronization A network gateway is configured to facilitate on line and off line bi-directional communication between a number of near end data and telephony devices with far end data termination devices via a hybrid fiber coaxial network and a cable modem termination system. The... | 04/04/2006 |
| 7020228 | DLL circuit A DLL (delay locked loop) circuit for outputting a phase lock signal having a predetermined phase relationship with an input signal. The DLL circuit has: a functional block having a constant-current source; and bias generator for generating a constant current source... | 03/28/2006 |
| 7016443 | Synchronization method and system for clock signal sources, in particular in packet transmission communication systems The invention relates to a method for synchronization of clock sources in a communications system, in particular a radio communications system, having a large number of devices (PSTN, MSC, RNM, BSi, MSi, OMC) which communicate directly or indirectly with one another... | 03/21/2006 |
| 7016354 | Packet-based clock signal In general, in one aspect, the disclosure describes a method for use in packet processing. The method can include receiving at least a portion of at least one packet and, based on the at least a portion of the at least one packet, determining a clock signal to provi... | 03/21/2006 |
| 7016448 | Synchronization state detector A system and method for reducing timing uncertainties in a serial data signal A system may comprise a transmitter configured to transmit serial data to a receiver through a transmission medium, e.g., wireless, wired. The receiver may comprise an oscillator configure... | 03/21/2006 |
| 7016449 | Timing recovery and frequency tracking system and method A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a f... | 03/21/2006 |
| 7016451 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 03/21/2006 |
| 7017065 | System and method for processing information, and recording medium To provide an integrated information processing unit that is capable of producing images and sounds of high quality. It includes a control unit, information processing units, and a merge unit. Each of the information processing units includes a counter for synchroni... | 03/21/2006 |
| 7012454 | Clock shift circuit for gradual frequency change A circuit for changing clocks includes a clock generating circuit which generates an output clock signal by controlling a frequency of an original clock signal, and a control circuit which controls the clock generating circuit in response to an operation mode change... | 03/14/2006 |
| 7012983 | Timing recovery and phase tracking system and method A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a f... | 03/14/2006 |
| 7013354 | Channel protocol for IEEE 1394 data transmission A system for transmitting and receiving data formatted in IEEE 1394 standard between devices using a same IEEE 1394 broadcast channel includes a CPU interfaced to a bus, a first 1394 interface connected to the bus via a first physical and link layers, and a second 1... | 03/14/2006 |
| 7010074 | Oversampling clock recovery having a high follow-up character using a few clock signals An oversampling clock recovery method according to this invention generates non-uniform three-phase clock signals CLKa, CLKb, and CLKc having non-uniform intervals for one bit of an input data i and controls phases of the clock signals so that either phase of two ed... | 03/07/2006 |
| 7010077 | Gated clock recovery circuit A gated clock recovery circuit is disclosed that receives an input data stream and generates a frequency and phase aligned clock output. The gated clock recovery circuit substantially instantaneously adjusts the generated clock signal to phase changes in the incomin... | 03/07/2006 |
| 7010370 | System and method for adjusting delay of an audio signal A method for adjusting a time delay between a first audio signal and a second audio signal is disclosed. The method includes generating the first audio signal from a buffer as a first data stream and generating the second audio signal from the buffer as a second dat... | 03/07/2006 |
| 7010014 | Digital spread spectrum circuitry The frequency of a skew clock signal is dithered around a base frequency, thereby enabling this clock signal to comply with FCC requirements for electromagnetic emissions within a specified window. Delay is introduced such that the clock signals exhibits slightly di... | 03/07/2006 |
| 7003064 | Method and apparatus for periodic phase alignment In one form, apparatus for aligning clock signals includes first and second logic circuitry for receiving respective first and second clock signals. The first and second clock signals are substantially synchronized and operations of the first logic circuitry and sec... | 02/21/2006 |
| 7002982 | Apparatus and method for storing data A method and apparatus for storing data, the method including the steps of generating a glitchless fractional clock pulse in a circuit and transmitting the glitchless fractional clock pulse from the circuit to a data storage element. The data storage element thereaf... | 02/21/2006 |
| 6999547 | Delay-lock-loop with improved accuracy and range A Delay-Lock-Loop circuit and a method for producing a phase shift comprises a phase generator producing a first and second clock signal having a first and second rising edge, respectively, wherein a timing difference between the first and second rising edges is equ... | 02/14/2006 |
| 6999544 | Apparatus and method for oversampling with evenly spaced samples The architecture and the method of operation of a receiver core are described. The core performs clock and data recovery on an incoming serial data stream transmitted across a wired media, such as a chip-to-chip or card-to-card interconnect. The bit error rate and a... | 02/14/2006 |
