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| Number | Title | Issue Date |
| 7577225 | Digital phase-looked loop Embodiments of the invention include an integrated circuit including a phase-locked loop (PLL). The integrated circuit includes a phase detector, a frequency detector, a loop filter, a digitally-controlled oscillator and a corresponding plurality of frequency divide... | 08/18/2009 |
| 7561652 | High frequency spread spectrum clock generation For EMI reduction the current modulation profile is preferably used for frequencies over 1 GHz while the frequency deviation is increased at least to ±2.5 MHz and the modulation frequency is increased to at least 150 kHz, preferably about 260 kHz. In an alternative... | 07/14/2009 |
| 7561653 | Method and apparatus for automatic clock alignment The present invention synchronizes signals generated and used in different clock domains. The invention is applicable to a CDR circuit in which phase adjustment of a multiphase clock to the phase of incoming data is implemented by controlling phase offsets from the ... | 07/14/2009 |
| 7486757 | Optical driver including a multiphase clock generator having a delay locked loop (DLL), optimized for gigahertz frequencies An optical (disc) driving system including the DLL based multiphase clock generator circuit capable of generating 32 different phases from input clock having a frequency of 800 MHz or greater. The multiphase clock generator includes on a delay locked loop (DLL) havi... | 02/03/2009 |
| 7477715 | Delay-locked loop circuit of a semiconductor device and method of controlling the same A delay-locked loop (DLL) circuit includes a standby signal generating circuit, a front stage circuit, and a back stage circuit. The standby signal generating circuit generates a first standby signal and a second standby signal in response to an active signal, a cro... | 01/13/2009 |
| 7460631 | Communication system with synchronization alliances In a communication system including nodes laid out in a grid, each node operates on a repetitive internal timing cycle, at certain phases in which the node transmits data and state variable signals. The state variable signals transmitted by a node indicate its inter... | 12/02/2008 |
| 7457391 | Clock and data recovery unit A clock and data recovery unit for recovering a received serial data bit stream having: phase adjustment means for adjustment of a sampling time in the center of a unit interval of the received data bit stream, wherein the phase adjustment means comprises means for ... | 11/25/2008 |
| 7443941 | Method and system for phase offset cancellation in systems using multi-phase clocks A system for use with a multi-phase clock generator is disclosed. It should also be understood that the multiphase clock generator can be a phase lock loop (PLL), delay lock loop (DLL), or any other circuit capable of providing a multiphase clock. The system compris... | 10/28/2008 |
| 7440533 | Modulated jitter attenuation filter A system and modulation method are provided for reducing jitter in the mapping of information into Synchronous Payload Envelopes (SPEs), in a data tributary mapping system. The method comprises buffering data from a plurality of tributaries, and generating buffer-fi... | 10/21/2008 |
| 7440518 | Phase-locked loop circuit A PLL circuit comprises a controller (DRC) adjusting the frequency of frequency modulated signals (uDIV) provided by a frequency modulator (DIV) on the basis of signals provided by a linear range detector (LRD) so that the phase detector gets back into a ... | 10/21/2008 |
| 7433392 | Wireless communications device performing block equalization based upon prior, current and/or future autocorrelation matrix estimates and related methods A wireless communications device may include a wireless receiver for receiving signals comprising alternating known and unknown symbol portions, and a demodulator connected thereto. The demodulator may include a channel estimation module for generating respective ch... | 10/07/2008 |
| 7433430 | Wireless communications device providing enhanced block equalization and related methods A wireless communications device may include a wireless receiver receiving signals having alternating known and unknown symbol portions over a channel, and a demodulator systolic array. The demodulator systolic array may include a channel estimation module generatin... | 10/07/2008 |
| 7433442 | Linear half-rate clock and data recovery (CDR) circuit A linear, half-rate clock and data recovery (CDR) circuit for recovering clock information embedded in a received data signal. The half-rate CDR circuit comprises a phase detector that may receive the data signal and generate a phase error signal representative of t... | 10/07/2008 |
| 7430264 | Method to reduce transient current swings during mode transitions of high frequency/high power chips A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances a... | 09/30/2008 |
| 7430680 | System and method to align clock signals A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer with a clock signal of a storage device before the sequencer transfers... | 09/30/2008 |
| 7428284 | Phase detector and method providing rapid locking of delay-lock loops A delay-lock loop includes a dual mode phase detector. The dual mode phase detector includes a single edge phase detector that generates output signals indicative of the phase relationship between the rising edge of a reference signal and the rising edge of a feedba... | 09/23/2008 |
| 7424068 | Method and system for coding/decoding signals and computer program product therefor A method for decoding signals with encoded symbols over a symbol interval that modulate a carrier. The method includes phase locking the signal to be decoded to obtain a phase-locked signal. The value assumed by the phase-locked signal on at least one subinterval in... | 09/09/2008 |
| 7424078 | Synchronous compensator adaptively defining an enable range for synchronous compensation In the synchronous compensator, a load generator loads a bit counter with data in dependence upon whether or not a detection signal from a UW detector falls within the range indicated by an enable signal from a synchronous compensator circuit, thereby excluding the ... | 09/09/2008 |
| 7424082 | Digital lock detector for PLL Circuits and methods for detecting a lock condition of a phase-locked loop (PLL) circuit are provided. A frequency divider outputs a clock having a frequency equal to a reference clock frequency divided by N. A counter counts the number (M) of clock edges of a PLL o... | 09/09/2008 |
| 7421042 | Carrier tracking loop lock detector An ATSC (Advanced Television Systems Committee) VSB (Vestigial Sideband) receiver includes a carrier tracking loop (CTL) for processing a received ATSC VSB signal and a CTL lock detector. The CTL lock detector includes an averaging filter for averaging the down-conv... | 09/02/2008 |
| 7421054 | Sampling clock generator circuit and data receiver using the same A sampling clock generator circuit comprises a ring oscillator including series-connected m first inverters connected to a first power supply line, where m is an odd number equal to or larger than 3, a delay line including series-connected 2m or 2m−1 second invert... | 09/02/2008 |
| 7418070 | Signal generator In a signal generator, a peak value/peak position detection section detects value and position of an amplitude peak observed in modulation data coming from an orthogonal modulation section, and a peak carrier extraction section extracts L subcarriers capable of mini... | 08/26/2008 |
| 7415092 | Low wander timing generation and recovery Systems, apparatuses, and methods for low wander timing generation and/or recovery are disclosed here. In one aspect, embodiments of the present disclosure include a communication system for high speed communications between a first location and a second location. T... | 08/19/2008 |
| 7412019 | Spread spectrum clock generator A spread spectrum clock generator comprising a phase-locked loop circuit and a modulation circuit. The phase-locked loop circuit receives a reference signal at a reference frequency and outputs an output signal at an output frequency periodically varying in a range ... | 08/12/2008 |
| 7409029 | Transmission device for automatically set an optimal point for a signal decision making There is provided a flexible transmission device capable of automatically setting an optimal point for a signal decision making with high accuracy, so that highly reliable high-quality signal regeneration control is achieved. A clock timing extraction circuit dynami... | 08/05/2008 |
| 7409028 | Clock synchronization in a communications environment A method and system provide a stable reference clock for use in a communication system. A phase-locked loop (PLL) receives an input clock signal with potentially unacceptable levels of jitter and wander. The PLL provides a synchronized output clock with significantl... | 08/05/2008 |
| 7400655 | Transmission device A transmission device which cross connects channels on a synchronous multiplex transmission network which forms a ring, and which performs restoration of communication by looping back signals in a protection path when a failure occurs includes a memory area which st... | 07/15/2008 |
| 7397881 | Erroneous phase lock detection circuit The present invention is concerned with a phase comparator circuit and provides an erroneous phase lock detection circuit that detects erroneous phase lock occurring when the duty cycle of data deviates from 100% in a comparison of a phase difference between the dat... | 07/08/2008 |
| 7397882 | Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase compar... | 07/08/2008 |
| 7391840 | Phase locked loop circuit, electronic device including a phase locked loop circuit and method for generating a periodic signal A phase locked loop (PLL) circuit (1) comprising a loop input (11); a phase detector section (2) for detecting a phase difference between an input signal and a reference signal. The phase detector section (2) has a detector input connected to th... | 06/24/2008 |
| 7391839 | Accumulator based phase locked loop There is disclosed a phase locked loop comprising: a phase frequency detector for receiving as a first input a reference signal and for generating a control signal; a voltage controlled oscillator for receiving the control signal and for generating a signal defining... | 06/24/2008 |
| 7391842 | Direct synthesis clock generation circuits and methods Clock signal generation circuitry includes input circuitry for receiving a frequency control input signal and a clock signal and generating a memory address therefrom, a memory for storing digital data indexed by the memory address and representing real and imaginar... | 06/24/2008 |
| 7382848 | First order tuning circuit for a phase-locked loop A first order phase-locked loop includes a tuning circuit which allows phase lock to be quickly reached, and to be maintained during transient situations such as loss of the data signal. Such an improved circuit has a tuning circuit for the voltage controlled oscill... | 06/03/2008 |
| 7382849 | Charge pump circuit Charge pump circuit. A charge pump circuit is provided for use in a phase-lock loop circuit. The charge pump circuit comprises a charge pump core circuit that outputs a control voltage. The charge pump circuit also comprises a replica circuit that is coupled to the ... | 06/03/2008 |
| 7375558 | Method and apparatus for pre-clocking A method and apparatus for pre-clocking have been disclosed. ... | 05/20/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7372932 | Locking-status judging circuit for digital PLL circuit A locking-status judging circuit is composed of a comparator that compares a phase error signal with a reference signal for judging whether or not a digital PLL circuit locks on an input signal and outputs a signal “0 (zero)” or a signal “1 (one)”, a selecto... | 05/13/2008 |
| 7372875 | Systems and methods for synchronization in asynchronous transport networks Techniques for synchronizing the clock of a local telecommunications network connected to a remote clock source through an asynchronous transport network such as an Ethernet metropolitan area transport network. A basic holdover loop for retaining the current reconst... | 05/13/2008 |
| 7369600 | Burst communications apparatus and method using tapped delay lines A communications apparatus and method use tapped delay lines as multiplexers and demultiplexers. In one embodiment, a receiver (100) uses a tapped delay line (110) as a demultiplexer to acquire a burst communication at very high data rates in the range... | 05/06/2008 |
| 7365532 | Apparatus to receive signals from electromagnetic coupler In at least one embodiment an apparatus is provided that includes an electromagnetic coupler probe to provide sampled electromagnetic signals and an electronics component to receive the sampled electromagnetic signals from the electromagnetic coupler probe and to pr... | 04/29/2008 |
