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| Number | Title | Issue Date |
| 6937679 | Spread spectrum clocking tolerant receivers In some embodiments, the invention includes a system having a clock recovery circuitry to receive a data signal and a reference clock signal and in response thereto to produce an in phase clock signal which is in phase with the data signal and mirrors frequency chan... | 08/30/2005 |
| 6937682 | Clock-pulse supply unit In a clock-pulse supply unit, a first receiver unit is used to tap a central system clock pulse from the back panel. A time delay occurs in the first receiver unit. In order to compensate this time delay, a second receiver unit is used which is identical in construc... | 08/30/2005 |
| 6934347 | Method for recovering a clock signal in a telecommunications system and circuit thereof Method for recovering a clock signal from an input data signal in a telecommunications system, that provides for comparing the input data signal with a recovered clock signal in order to control said recovered clock signal generation and provides for generating a pl... | 08/23/2005 |
| 6933761 | Techniques for dynamically selecting phases of oscillator signals Techniques for dynamically shifting the phase of clock signals are provided. A circuit generates a plurality of periodic clock signals. Each clock signal has the same period, the same duty cycle, and a different phase. The clock signals are provided to the inputs of... | 08/23/2005 |
| 6934348 | Device for recovering burst-mode optical clock Disclosed is a device for recovering a burst-mode clock. The burst-mode clock recovery device includes a delay unit and a logic element. A reference clock is produced by implementing a logic operation with respect to a signal output from signal forming device and a ... | 08/23/2005 |
| 6931075 | Event detection with a digital processor A bistable memory device changes logic state each time an event occurs. The bistable memory device has an logic output coupled to a digital processor input. The digital processor reads the logic state of the bistable memory device from its logic output and compares ... | 08/16/2005 |
| 6930995 | Apparatus and method for synchronization in a multiple-carrier communication system by observing a plurality of synchronization indicators A method, apparatus and system detects a loss of synchronization between a transmitter and a receiver in a multiple-carrier communication system such as an OFDM system. A plurality of synchronization indicators are observed to determine whether a loss of synchroniza... | 08/16/2005 |
| 6930525 | Methods and apparatus for delay circuit An electronic system includes a deskewing circuit configured to measure a delay and generate a synchronized signal according to the measured delay. The deskewing circuit may be configured to detect an overflow condition and respond accordingly, for example by assert... | 08/16/2005 |
| 6931086 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 08/16/2005 |
| 6920622 | Method and apparatus for adjusting the phase of an output of a phase-locked loop An integrated circuit receives a request to adjust the phase of an output clock being generated by a phase-locked loop based on an input reference clock. A digital or analog offset value is injected into the phase-locked loop based on a phase adjustment amount conta... | 07/19/2005 |
| 6917659 | Method and apparatus for receiving data A method of recovering data from a modulated data signal includes tracking a transmitted clock with a plurality of locally-generated clock phases, estimating an average phase of previously detected edges, registering a pulse edge in the received stream of data at a ... | 07/12/2005 |
| 6917228 | Delay locked loop circuit with time delay quantifier and control A delay locked loop circuit has a quantifier for obtaining a measured delay quantity based on a time delay between an external signal and an internal signal. Based on the measured delay quantity, a delay controller controls a correction delay quantity applied to a s... | 07/12/2005 |
| 6917660 | Adaptive de-skew clock generation A signal delay circuit that compensates for other delays introduced within the signal delay circuit itself. A delay-locked loop may produce multiple delayed clock signals, each having a defined phase difference with respect to, and representing a different delay fro... | 07/12/2005 |
| 6914953 | Multiphase clock recovery using D-type phase detector A method of extracting a clock signal from a data stream, by generating a plurality of multiphase clock signals, selecting one of the multiphase signals based on synchronization states identifying which of the multiphase clock signals is most closely aligned with th... | 07/05/2005 |
| 6914935 | Fractional N synthesizer with reduced fractionalization spurs A fractional N synthesizer is disclosed. The synthesizer includes a phase detector that receives first and second input signals and generates a pulse width modulated (PWM) output signal having a pulse width indicative of the phase relationship between the input sign... | 07/05/2005 |
| 6911851 | Data latch timing adjustment apparatus In a data latch timing adjustment apparatus, a read control section reads out a first checking data piece in a checking data storing section written in a memory and outputs a latch pulse signal to a delay selecting section. A selection part outputs, to a latch circu... | 06/28/2005 |
| 6911843 | Data transfer device for transferring data between blocks of different clock domains The number of pulses of a clock signal CLK-A is circularly counted in a count range from “0” to “7”, and count signals indicating count values are produced. A clock signal CLK-B having a frequency lower than that of the clock signal CLK-A is produced from co... | 06/28/2005 |
| 6912380 | PLL circuit and wireless mobile station with that PLL circuit In a PLL circuit, and a wireless mobile station with that PLL circuit, an LPF charging constant current source, a discharging constant current source and a high-speed charging constant current source are connected to an output terminal of a phase comparator with cur... | 06/28/2005 |
| 6909301 | Oscillation based access time measurement An embodiment of the invention is a method for measuring access time where the frequency of a ring oscillator is measured with and without a device under test 1 in the ring. Those two frequencies are compared to calculate the access time of the device under t... | 06/21/2005 |
| 6907095 | Clock ride-over method and circuit A clock ride-over circuit in which clock ride-over may be achieved even if jitter is contained in clocks prior to and subsequent to ride-over and no control input signal for write and readout is applied from outside. A clock prior to rideover CLK—1 | 06/14/2005 |
| 6907066 | Arrangement for reducing transmitted jitter A pulse transmitter includes a phase correction module configured for detecting a phase error between a transmit clock and a prescribed clock specification at a transmit clock instance. The transmit clock instance represents an instance in time in which the pulse tr... | 06/14/2005 |
| 6904475 | Programmable first-in first-out (FIFO) memory buffer for concurrent data stream handling A programmable FIFO receives a stream of data to be buffered within the FIFO and then output from the FIFO. The programmable FIFO includes the ability to receive program instructions from an application or control circuit to perform specific operations on the stream... | 06/07/2005 |
| 6904537 | Data transmission across asynchronous time domains using phase-shifted data packet A method and apparatus is provided for transmitting multi-bit data across asynchronous time domains. In one embodiment, the apparatus includes a first delay circuit to generate a selector signal based upon an input reference signal of a first time domain, a second d... | 06/07/2005 |
| 6901126 | Time division multiplex data recovery system using close loop phase and delay locked loop A time division multiplex data recovery system using a closed-loop phase lock loop (PLL) and delay locked loop (DLL) is disclosed. In other words, one closed loop comprises both a phase locked loop (PLL) and a delay locked loop (DLL) in a novel time division multipl... | 05/31/2005 |
| 6891420 | Method and apparatus for digital frequency synthesis A digital frequency synthesizer includes one or more reference clocks (104, 1316, 1502A, 1504A, 1506A) optionally coupled through one or more pulse width reducers (106) to one or more main delay lines (108, 702, 1502B, 1504B... | 05/10/2005 |
| 6888580 | Integrated single and dual television tuner having improved fine tuning Improved television tuning circuits are disclosed. An example tuning circuit includes a fraction-N frequency synthesizer facilitating fine tuning. This tuning circuit may be formed using relatively few independent oscillators. The tuning circuit lends itself to the ... | 05/03/2005 |
| 6873668 | Clock recovery circuit A feed-forward controlled phase difference detector for detecting a phase difference using the output of a comparator included in an analog-to-digital converter, for example, is combined with a known digital feedback controlled phase difference detector for recoveri... | 03/29/2005 |
| 6870410 | All digital power supply system and method that provides a substantially constant supply voltage over changes in PVT without a band gap reference voltage An all digital power supply system provides a supply voltage to semiconductor circuits. The power supply system utilizes an up/down counter and a pulse width modulator to output a signal into a LC network that generates the supply voltage. The width of the pulses ou... | 03/22/2005 |
| 6859509 | Wide bandwidth phase-locked loop circuit A PLL circuit uses a multiple frequency range PLL in order to phase lock input signals having a wide range of frequencies. The PLL includes a VCO capable of operating in multiple different frequency ranges and a divider bank independently configurable to divide the ... | 02/22/2005 |
| 6856170 | Clock signal transmission circuit A clock generator (10a) outputs either a first clock signal or a second clock signal. The second clock signal is higher in frequency than the first clock signal. Under control of a control signal (CNTL1), when the first clock signal and the seco... | 02/15/2005 |
| 6853696 | Method and apparatus for clock recovery and data qualification A system for recovering a clock signal from a data signal is described. The system uses an oscillator adapted to generate an oscillator output signal, a first detecting circuit for obtaining a coarse frequency-lock condition between the data signal and a recovered c... | 02/08/2005 |
| 6853695 | System and method for deriving symbol timing A symbol timing derivation system derives receiver timing from received symbols which avoids the need for a pilot tone, thereby reducing power consumption and expanding usable bandwidth. The system is implemented by using a calculation that finds the timing phase er... | 02/08/2005 |
| 6839388 | System and method for providing frequency domain synchronization for single carrier signals There is disclosed an improved system and method for providing frequency domain synchronization for a single carrier signal such as a vestigial sideband signal. The system comprises a synchronization circuit that is capable of obtaining a coarse frequency estimate o... | 01/04/2005 |
| 6826246 | Phase locked loop with control voltage centering A phase-locked loop (PLL) with reduced jitter is provided. The PLL includes dual path voltage-controlled oscillator inputs, with a control voltage from a loop filter sent through a low gain path and an integrated error voltage sent through a high gain path. The erro... | 11/30/2004 |
| 6807244 | Frequency synthesizer The invention proposes a frequency synthesizer for generating an output signal having a frequency associated with that of a reference clock, in which a control oscillating circuit generates a clock signal group including a plurality of clock signals having a phase d... | 10/19/2004 |
| 6807245 | PLO device There is provided a PLO device which performs high-accuracy, high-quality clock recovery. A shifted data generation part generates shifted data, and a first phase comparison part outputs first difference data. A first filter removes an alternating-current component ... | 10/19/2004 |
| 6807243 | Delay clock generating apparatus and delay time measuring apparatus A standard clock 34 is input to a phase comparator 52 and a phase controller 56. The ring oscillator 50 oscillates a shift clock 70 having a same cycle as the standard clock 34. The phase comparator 52 matches the dow... | 10/19/2004 |
| 6804318 | System and method for using a network timing reference circuit as a phase detector in a synchronization loop An improvement to system clock synchronization corrector in a digital transceiver allows the generation of a phase error correction signal for use in an imbedded clock synchronization control loop without the use of additional transmitted information or additional e... | 10/12/2004 |
| 6801591 | Clock recovery An exemplary data processing device includes a clock recovery system for locking a clock frequency to time stamps (PCR) of an incoming data stream, e.g. MPEG. The exemplary device uses a free running clock (20) that generates a reference frequency (FREF) from... | 10/05/2004 |
| 6798858 | Lock detector for delay or phase locked loops The present invention discloses a lock indicator circuit used to indicate a phase lock condition between logic signals. The lock indicator circuit uses a phase detector that generates a pulse width proportional to the phase difference between a reference signal and ... | 09/28/2004 |
