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| Number | Title | Issue Date |
| 8116419 | Methods and apparatuses for estimating time delay and frequency offset in single frequency networks In one method, an uplink signal carrying at least one block of transmitted samples is transmitted, and a distorted copy of the uplink signal is received as a downlink signal. A plurality of blocks of received samples are generated based on the received downlink sign... | 02/14/2012 |
| 8116418 | Fast locking clock and data recovery A clock data recovery comprises a phase detector, a phase interpolator, an initial phase detector, and an initial phase decoder. The phase detector receives an incoming data stream and an interpolated clock signal and output an early/late value indicating timing rel... | 02/14/2012 |
| 8116420 | Clock-forwarding technique for high-speed links A repeater circuit, such as a clock regeneration and multiplication circuit, is described. In this repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on a forwarded clock signal, which is received on a link. Furthermore, a phase... | 02/14/2012 |
| 8107579 | Configurable baseband in a GPS receiver Clock compensation for GPS receivers. A receiver in accordance with the present invention comprises a Radio Frequency (RF) portion, and a baseband portion, coupled to the RF portion, wherein the baseband portion comprises a crystal, an oscillator, coupled to the cry... | 01/31/2012 |
| 8102960 | Adaptation of a digital receiver A method and apparatus to improve adaptation speed of a digital receiver is presented. The receiver includes an equalizer to initiate adaptation to a transmission channel responsive to a first control signal, a slicer coupled to the equalizer to generate symbol deci... | 01/24/2012 |
| 8085892 | Offset determination arrangement, offset compensation arrangement, synchronization clock generator, method for determination of an offset and modulation method An offset determination arrangement includes a comparator device to compare an input signal with a reference value. A synchronization unit is provided to forward a comparison result of the comparator device as a function of a synchronization signal which can be gene... | 12/27/2011 |
| 8073092 | Automatic synchronization of an internal oscillator to an external frequency reference An internal integrated circuit clock oscillator is automatically synchronized to an external frequency reference by counting the number of periods of the internal clock oscillator (hereinafter “count”) that occur within a period of a lower frequency external fre... | 12/06/2011 |
| 8050375 | Digital phase locked loop with integer channel mitigation An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF ... | 11/01/2011 |
| 8019036 | Method and apparatus for correcting sampler clock frequency offset in OFDM MIMO systems In an orthogonal frequency division multiplexed (OFDM) multiple-in multiple-out (MIMO) wireless communication system, a method for correcting sampler clock frequency offset in a receiver comprises acquiring the frequency offset and symbol timing in a received signal... | 09/13/2011 |
| 8005182 | Apparatus and method of compensating for frequency offset in OFDMA system The present invention relates to an apparatus and method of compensating for a frequency offset in an orthogonal frequency division multiple access system that is capable of efficiently estimating and compensating for the frequency offset. A receiver of the orthogon... | 08/23/2011 |
| 8005181 | Clock and clock adjustment circuit for minimum jitter A method for adjusting a clock for a jitter sensitive circuit begins by determining a low noise phase region of a primary clock. The method then continues by adjusting phase of an auxiliary clock such that a transition of the auxiliary clock falls within the low noi... | 08/23/2011 |
| 7970254 | PLL control circuit of optical disc apparatus, and recording medium having recorded thereon program for controlling the optical disc apparatus A PLL control circuit of an optical disc apparatus comprising: a voltage frequency conversion circuit that adjusts an oscillating frequency based on a control voltage to generate a first frequency signal; a phase comparison circuit that compares the phase of the fir... | 06/28/2011 |
| 7949080 | Phase adjusting function evaluating method, transmission margin measuring method, information processing apparatus and computer readable information recording medium A phase amount added to a clock signal or a plurality of data signals for adjusting a phase relationship therebetween in a reception apparatus is changed, and, a result of the phase adjusting operation is stored when the phase amount added to the clock signal or the... | 05/24/2011 |
| 7924964 | Receiver with the function of adjusting clock signal and an adjusting method therefor A receiver having a first clock signal is provided. The first frequency of the first clock signal is adjusted to be close to a second frequency of a second clock signal of a transmitter. The receiver includes a clock generator, a processor and a controller. The cloc... | 04/12/2011 |
| 7916822 | Method and apparatus for reducing latency in a clock and data recovery (CDR) circuit Disclosed is a system and method for a clock and data recovery (CDR) circuit. A phase selection circuit (PSC) generates a signal comprising frequency and phase. A voltage controlled oscillator (VCO) connected to the PSC generates a clock signal. The clock signal con... | 03/29/2011 |
| 7916821 | Method and apparatus for output data synchronization with system clock in DDR A method and apparatus are provided for substantially reducing or eliminating the timing skew caused by delay elements in a delay locked loop. A method and apparatus are disclosed wherein a rising edge of a local timing signal is established and phase-locked to a ri... | 03/29/2011 |
| 7885367 | System for adjusting sampling timing of DLL circuit, method therefor and transmitter-receiver used therefor An object of the present invention is to provide a DLL circuit adjustment system that can adjust the sampling timing of a DLL circuit without causing any increase of the number of interface signals or amount of coding overhead and any reduction of the data transfer ... | 02/08/2011 |
| 7844023 | Phase offset cancellation for multi-phase clocks A system for use with a multi-phase clock generator is disclosed. It should also be understood that the multiphase clock generator can be a phase lock loop (PLL), delay lock loop (DLL), or any other circuit capable of providing a multiphase clock. The system compris... | 11/30/2010 |
| 7826581 | Linearized digital phase-locked loop method for maintaining end of packet time linearity An apparatus and method are disclosed synchronization of a clock signal to a data signal. The apparatus includes a phase lock and tracking logic circuit configured to detect a plurality of values. Each of the plurality of values indicates a position of a data edge o... | 11/02/2010 |
| 7796719 | Signal detection apparatus and method thereof The invention discloses a signal detection apparatus and method thereof for detecting whether an input signal of a set of serial ATA signals is an out of band (OOB) signal. The signal detection apparatus includes a calibrated clock generation device, a signal proces... | 09/14/2010 |
| 7773713 | Clock data recovery systems and methods for direct digital synthesizers A system and method for clock data recovery for programming direct digital synthesizers is disclosed. A counter is used to calculate a coarse measurement of the clock frequency of a received digital signal, and a tap delay line is used to calculate a fine measuremen... | 08/10/2010 |
| 7756235 | Methods and apparatus for digital compensation of clock errors for a clock and data recovery circuit Methods and apparatus are provided for digital compensation of clock timing errors in a VCDL. Clock timing errors in a clock and data recovery system having a voltage controlled delay loop comprised of a plurality of delay elements are compensated for by evaluating ... | 07/13/2010 |
| 7751520 | Packet detection, synchronization, and frequency offset estimation Techniques are disclosed for detecting a packet. One technique includes sampling a received signal to produce a sequence of samples wherein the sequence of samples includes a plurality of subsequences of samples; cross correlating the subsequences of samples with a ... | 07/06/2010 |
| 7738617 | Clock and data recovery locking technique for large frequency offsets Techniques and apparatus for a clock and data recovery circuit to lock to data having frequency offsets relative to a local clock reference are disclosed. One embodiment includes a multi-step frequency tracking system in which each step is used to track a sub-range ... | 06/15/2010 |
| 7733999 | System and method for an adaptable timing recovery architecture for critically-timed transport applications The present invention provides a timing recovery architecture and circuit for recovering the clock timing from a received signal in critically-timed transport applications. The present invention further relates to a timing recovery architecture and circuit for remov... | 06/08/2010 |
| 7706495 | Two-point frequency modulation apparatus A two-point frequency modulation apparatus is proposed whereby the spectrum of transmission waves is kept within the spectrum mask. Voltage is supplied to the control voltage terminal of VCO 1 in accordance with modulation data via noise shaper 101 tha... | 04/27/2010 |
| 7697651 | Lock system and method for interpolator based receivers A tracking loop of an interpolator based receiver includes clock elements that generate a plurality of clocks to sample a signal from a remote transmitter. The tracking loop includes samplers and voter elements that sample the signal with the clocks and generate sam... | 04/13/2010 |
| 7676011 | Data recovery apparatus and method for reproducing recovery data A data recovery apparatus and method for receiving at least an original clock and at least an original data stream output from a transmitter to output at least one recovery data are provided. The original data stream and the recovery data respectively include N step... | 03/09/2010 |
| 7668277 | Apparatus and method for clock data recovery with low lock frequency For clock and data recovery (CDR), a clock processor generates sampling clock signals from original phase-shifted clock signals each having a frequency that ⅛ of a frequency of an input data signal. The sampling clock signals are used to sample the input data sign... | 02/23/2010 |
| 7656984 | Circuits and methods for recovering a clock signal A circuit for recovering a clock signal may include a frequency multiplier configured to generate a plurality of local clock signals, each having a different phase, based on a plurality of received global clock signals at a first frequency and each having a differen... | 02/02/2010 |
| 7656985 | Timestamp-based all digital phase locked loop for clock synchronization over packet networks A timestamp-based all digital phase locked loop is utilized for clock synchronization for Circuit Emulation Service (“CES”) over packet networks. The all digital phase locked loop at a CES receiver includes a phase detector, a loop filter, a digital oscillator a... | 02/02/2010 |
| 7653168 | Digital clock dividing circuit Disclosed is a digital dividing circuit for dividing a timing signal. Memory elements are disposed in opposed pairs at opposed sides of a data loop. Each memory element is clocked to change the data bit it stores on each clock pulse. At least two opposed nodes along... | 01/26/2010 |
| 7599461 | Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data in the presence of an adverse pattern Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data, in the presence of an adverse pattern, such as a Nyquist pattern. A received signal is sampled using a data clock and a transition ... | 10/06/2009 |
| 7599460 | Transmitting apparatus A device including a line interface for additionally installing a line is installed in a terminal repeater device which takes a work and protection redundancy configuration based on a criterion such as SONET, SDH, or the like. Within the device additionally installe... | 10/06/2009 |
| 7580496 | Device for receiving series data A circuit for receiving digital data arriving in series comprising a circuit for generating a reference dock and a circuit for oversampling the received data memorizing the samples sampled at the rate of several clocks phase-shifted with respect to the reference clo... | 08/25/2009 |
| 7577224 | Reducing phase offsets in a phase detector In one embodiment, the present invention includes a system having an amplifier to receive an incoming signal and a recovery circuit coupled to the amplifier that includes a phase detector to adjust a phase of a sampling clock via a signal indicative of a difference ... | 08/18/2009 |
| 7577225 | Digital phase-looked loop Embodiments of the invention include an integrated circuit including a phase-locked loop (PLL). The integrated circuit includes a phase detector, a frequency detector, a loop filter, a digitally-controlled oscillator and a corresponding plurality of frequency divide... | 08/18/2009 |
| 7561652 | High frequency spread spectrum clock generation For EMI reduction the current modulation profile is preferably used for frequencies over 1 GHz while the frequency deviation is increased at least to ±2.5 MHz and the modulation frequency is increased to at least 150 kHz, preferably about 260 kHz. In an alternative... | 07/14/2009 |
| 7561653 | Method and apparatus for automatic clock alignment The present invention synchronizes signals generated and used in different clock domains. The invention is applicable to a CDR circuit in which phase adjustment of a multiphase clock to the phase of incoming data is implemented by controlling phase offsets from the ... | 07/14/2009 |
| 7486757 | Optical driver including a multiphase clock generator having a delay locked loop (DLL), optimized for gigahertz frequencies An optical (disc) driving system including the DLL based multiphase clock generator circuit capable of generating 32 different phases from input clock having a frequency of 800 MHz or greater. The multiphase clock generator includes on a delay locked loop (DLL) havi... | 02/03/2009 |
