Quotables
"I watched his countenance closely, to see if he was not deranged ... and I was assured by other senators after he left the room that they had no confidence in it."
U.S. Senator Smith of Indiana ; After seeing Samuel Morse demonstrate the telegraph.
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| Number | Title | Issue Date |
| 6941445 | Resampling address generator A resampling address generator updates period data in a resampling period address register when the periods of input and output clocks are not stable, and generates a read address by supplying the output of a register to an accumulative adder. When the periods of th... | 09/06/2005 |
| 6937621 | Apparatus and method for determining byte gain and loss adjustments in a SONET/SDH network element An apparatus and method determine byte gain and loss adjustments that compensate for frequency differences between ingress and egress data rate signals in a SONET/SDH NE. The count of ingress data rate signal pulses at the time that data is requested by a switch fab... | 08/30/2005 |
| 6937613 | Method and apparatus for synchronization of high-bit-rate digital subscriber line signals Timing information, such as stratum 1 traceable synchronization information, is transmitted in a high-bit-rate digital subscriber line (HDSL) transport frame by timing the transport frame using a corresponding timing reference signal. In an illustrative embod... | 08/30/2005 |
| 6934296 | Packet transfer device and packet transfer method adaptive to a large number of input ports A packet transfer device that can be easily realized even when a number of input ports is large. Each input buffer temporarily stores entered packets class by class, and outputs packets of a selected class specified by the control unit, while the control unit determ... | 08/23/2005 |
| 6931029 | System and method for synchronizing with data received over an unreliable asynchronous medium A system for re-establishing synchrony with data that was synchronous data in a source device but for which synchrony is lost when the data is transmitted over an asynchronous and unreliable medium to a destination device. The system includes buffering of the data r... | 08/16/2005 |
| 6928094 | Laser driver circuit and system A laser driver circuit to provide a current signal to power a laser device is described. A bias current provided to the laser device may be changed while changes in the output power of a light signal from the laser device is monitored. A slope efficiency associated ... | 08/09/2005 |
| 6928129 | Phase locked loop circuit and method of frequency modulation in phase locked loop circuit The present invention provides a phase locked loop circuit comprising: a frequency divider for frequency-diving an output signal to generate frequency-divided pulses; an oscillator for generating the output signal under control to an oscillation frequency by a contr... | 08/09/2005 |
| 6928387 | Circuit and method for distributing events in an event stream A circuit and method for distributing events in an event stream. A circuit for distributing events in a signal into a plurality of channels of circuitry capable of timestamping events is described. The circuit includes a first plurality of flip-flops arranged in a c... | 08/09/2005 |
| 6928126 | Reception interface unit in transmission system A reception interface unit in a transmission system wherein time series data is divided into data groups and a data packet with reproduction specification time data specifying a time at which each data piece in the data groups should be reproduced, added to the data... | 08/09/2005 |
| 6922749 | Apparatus and methodology for an input port of a switch that supports cut-through operation within the switch An input port is described having an input policing unit that checks if a virtual lane has a sufficient number of credits to carry an input packet received by the input policing unit. The input port also has a request manager that generates a request for the packet ... | 07/26/2005 |
| 6917366 | System and method for aligning multi-channel coded data over multiple clock periods A system and method is provided for aligning multi-channel coded data over multiple clock periods. Data is received through a plurality of data channels and stored in a plurality of latches or queues. Data is scanned to determine whether a valid data transition has ... | 07/12/2005 |
| 6917247 | NCO based timebase recovery system and method for A/V decoder Systems and methods are disclosed for recovering a clock or time reference for A/V systems. One method comprises receiving at least one input time reference generated using a first clock and generating, using a second clock asynchronous to the first clock, at least ... | 07/12/2005 |
| 6914901 | System and method for communicating using multiple memory banks A method for communicating data is provided that includes communicating a first set of data from a first channel to a first serial-to-parallel converter and communicating a second set of data from a second channel to a second serial-to-parallel converter, the data s... | 07/05/2005 |
| 6912602 | System having two or more packet interfaces, a switch, and a shared packet DMA circuit An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmittin... | 06/28/2005 |
| 6910145 | Data transmission across asynchronous clock domains In one embodiment of the present invention, a system is provided for use in transmitting data and related control information from a first clock domain to a second clock domain. The system may include a first logic section that may generate respective identification... | 06/21/2005 |
| 6907066 | Arrangement for reducing transmitted jitter A pulse transmitter includes a phase correction module configured for detecting a phase error between a transmit clock and a prescribed clock specification at a transmit clock instance. The transmit clock instance represents an instance in time in which the pulse tr... | 06/14/2005 |
| 6907541 | System for recovering received data with a reliable gapped clock signal after reading the data from memory using enable and local clock signals A system for reliably receiving data includes a memory, write logic, and read logic. The write logic receives data and an unreliable clock signal and writes the data to the memory using the unreliable clock signal. The read logic generates a gapped clock signal and ... | 06/14/2005 |
| 6903587 | Clock data recovery circuit with improved jitter transfer characteristics and jitter tolerance A clock extracting part has a first phase comparator circuit, a first up/down counter, a weighting circuit, a charge pump and a low-pass filter forming a voltage value determining part, and a voltage controlled oscillator circuit. A retiming clock generating part ha... | 06/07/2005 |
| 6904475 | Programmable first-in first-out (FIFO) memory buffer for concurrent data stream handling A programmable FIFO receives a stream of data to be buffered within the FIFO and then output from the FIFO. The programmable FIFO includes the ability to receive program instructions from an application or control circuit to perform specific operations on the stream... | 06/07/2005 |
| 6904053 | Fibre Channel switching fabric The Fibre. Channel standard was created by the American National Standard for Information Systems (ANSI) X3T11 task group to define a serial I/O channel for interconnecting a number of heterogeneous peripheral devices to computer systems as well as interconnecting t... | 06/07/2005 |
| 6894727 | Picture transmission apparatus, a picture transmission method and a recording medium, and a picture transmission program Providing picture transmission apparatus, a picture transmission method and a recording medium, and a picture transmission program that can transmit the latest picture data in real time depending on the situation of the network bandwidth. The aforementioned picture ... | 05/17/2005 |
| 6885217 | Data transfer control circuitry including FIFO buffers Data transfer control circuitry includes a receive buffer for sequentially receiving received data, which are provided from a local processor together with a write control signal to store the data therein, and sequentially developing the stored data in response to a... | 04/26/2005 |
| 6882662 | Pointer adjustment wander and jitter reduction apparatus for a desynchronizer An apparatus for reducing the effects of pointer adjustments, wander, and jitter during desynchronization of a non-uniformly gapped data stream from a payload of a synchronized signal is disclosed. The apparatus utilizes a combination of two pointer adjustment signa... | 04/19/2005 |
| 6876710 | Digitally controlled circuit for reducing the phase modulation of a signal A digitally controlled circuit for reducing the phase modulation of a signal. The circuit has a multiphase clock generator that produces n phases of a clock that is m-times the signal. The circuit further has a multiplexer with n inputs for the n phases of the clock... | 04/05/2005 |
| 6865241 | Method and apparatus for sampling digital data at a virtually constant rate, and transferring that data into a non-constant sampling rate device An improved data acquisition system interface provides virtually constant sampling of input signals and provides those signals in a digitized format to a data acquisition unit that may not be able to sample at a constant rate without missing or “losing” some of ... | 03/08/2005 |
| 6865222 | Method and apparatus for testing a serial transmitter circuit An integrated circuit (12) contains a serializing transmitter, including a phase locked loop (31) that supplies seven clocks (41) with different phases to a serializer circuit (32). The serializer circuit accepts 7-bit words at a parallel... | 03/08/2005 |
| 6859153 | Method and apparatus for changing the rate of time-discrete signals Methods and apparatus are provided for changing the rate of time-discrete signals. When changing the rate or for the interpolation of time-discrete input values (xn), output values (yk) of an output signal are produced. If the frequency of the output signal is great... | 02/22/2005 |
| 6853695 | System and method for deriving symbol timing A symbol timing derivation system derives receiver timing from received symbols which avoids the need for a pilot tone, thereby reducing power consumption and expanding usable bandwidth. The system is implemented by using a calculation that finds the timing phase er... | 02/08/2005 |
| 6853696 | Method and apparatus for clock recovery and data qualification A system for recovering a clock signal from a data signal is described. The system uses an oscillator adapted to generate an oscillator output signal, a first detecting circuit for obtaining a coarse frequency-lock condition between the data signal and a recovered c... | 02/08/2005 |
| 6819727 | Method and device for the numeric control of the buffer and of a phase-locked loop for asynchronous networks A method and device is described for the numeric control of buffer and phase-locked loop for the recovery of the synchronism and the optimized management over communication networks having a high jitter like, e.g., networks in which the ATM mode (Asynchronous Transf... | 11/16/2004 |
| 6819725 | Jitter frequency shifting Δ-Σ modulated signal synchronization mapper A signal synchronization mapper for mapping an input data stream characterized by a first frequency (typically a SONET/SDH stream) into an output data stream characterized by a second frequency. A phase lock control loop containing a “delta-sigma” (Δ-Σ) modula... | 11/16/2004 |
| 6819732 | Asynchronous sample rate estimation using reciprocal frequency error minimization An asynchronous sample rate estimator and a method for generating a rate estimate to track an asynchronous input sampled signal is disclosed. The present invention achieves lock quickly and maintains an optimum input buffer configuration and enhanced signal fidelity... | 11/16/2004 |
| 6819730 | Filtering method for digital phase lock loop A filtering method for digital phase lock loop, comprises defining an ideal phase difference value between an input clock and a local recovery clock; calculating a phase difference between the input clock and the local recovery clock by a subtractor; and comparing t... | 11/16/2004 |
| 6816504 | Method and apparatus for transferring deterministic latency packets in a ringlet Briefly, in accordance with one embodiment of the invention, a method of using a bypass buffer in a node coupled to a ringlet includes the steps of: writing a packet of binary digital signals on the ringlet into the bypass buffer; and retaining the packet of binary ... | 11/09/2004 |
| 6810098 | FIFO read interface protocol An apparatus configured to interface a first clock speed of a multiqueue storage device and a second clock speed of an interface. The apparatus may be configured to control a flow of variable size data packets. ... | 10/26/2004 |
| 6807638 | Apparatus for and method of in-band clock compensation A novel and useful apparatus for and method of in-band clock compensation for use in synchronous communication systems. The clock compensation mechanism is implemented in each module and is operative to compensate for the differences between the clocks among the var... | 10/19/2004 |
| 6782067 | Asynchronous data reception circuit of a serial data stream Data reception circuit for receiving a serial input data stream, where the data reception circuit has a data stream separation circuit (4) for separating the serial input data stream into a plurality of separate data streams, a reference clock signal generati... | 08/24/2004 |
| 6778620 | Method and an arrangement for preventing metastability A system and method of preventing metastability in conjunction with the receipt in a first clock domain of an asynchronous digital signal from a second clock domain when the first domain operates with a first clock frequency, and the second domain operates with a se... | 08/17/2004 |
| 6775724 | Method and apparatus for synchronization control for various frequencies A synchronization control apparatus and method enables synchronization control which can flexibly accommodate various frequencies using a simple circuit construction. A storage device that has a predetermined capacity, such as a FIFO, stores externally input data. A... | 08/10/2004 |
| 6757342 | Data demodulation A data demodulating technique for binary data defined by a pulse code modulated signal. The technique involves digitizing the data signal read by a magnetic head from the stripe of a magnetic card. The time interval between peaks in the digitized signal is determine... | 06/29/2004 |
