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...that the first rickshaw was invented in 1869 by an American Baptist minister, the Rev. E. Jonathan Scobie, to transport his invalid wife around the streets of Yokohama?
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| Number | Title | Issue Date |
| 7355378 | Source synchronous sampling There is provided a method of source synchronous sampling, where a first clock signal of a first unit is synchronized to a second signal received from a second unit. The method includes determining a timing control signal on the base of the first clock signal and th... | 04/08/2008 |
| 7356789 | Metastability effects simulation for a circuit description A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in ... | 04/08/2008 |
| 7356036 | Method providing distribution means for reference clocks across packetized networks Disclosed is a method of distributing a number of reference clocks across a packet network. The packet network has a master node and one or more slave nodes, the master node and each slave node having basis clocks. A sender sends time-stamped synchronization packets... | 04/08/2008 |
| 7356727 | Electronic device employing efficient fault tolerance Disclosed herein is an electronic device capable of providing efficient fault-tolerance update processes by employing a backup memory block used in conjunction with a block-by-block update process, wherein the backup memory block may be employed to store backup cont... | 04/08/2008 |
| 7356101 | Apparatus and a method for calculation of a correlation value corresponding to a frequency error, and a recording medium with a recorded correlation value calculation program An apparatus for calculation of correlation that can take a correlation even when a frequency error is relatively large. With a 0-th degree correlator for taking, to output, a correlation between a reference signal and a measurement signal, an n-th degree correlator... | 04/08/2008 |
| 7356106 | Clock and data recovery circuit A clock and data recovery (CDR) circuit comprises a phase detector (PD) and a quadrature phase (QP) detector. A frequency detector (FD) is coupled to the PD and QP detector. The FD detects frequency difference between the output signals of the PD and QP detector and... | 04/08/2008 |
| 7352802 | System and method for controlling line driver power in digital subscriber line modems A low power DSL modem transmitter, suitable for incorporation in integrated DSLAM server line cards, transmits full power physical frames which include a control channel and a data field when data is available for transmission and physical frames having only a contr... | 04/01/2008 |
| 7353447 | System and method for representing compressed information The present invention provides a system and method for storing re-synchronization, error correction and/or error detection data within an existing communication protocol, while still maintaining full compliance to a standard, such as the MPEG-2 AAC standard. By doin... | 04/01/2008 |
| 7353417 | Microcontroller with synchronised analog to digital converter A microcontroller is provided, which includes a control unit (UC), at least one digital to analog converter (DAC) as a peripheral of the said control unit, and a buffer register located between the said control unit and the said converter, receiving data and a first... | 04/01/2008 |
| 7352715 | Time synchronization using dynamic thresholds Methods and apparatus for time synchronization using dynamic thresholds. A method for synchronizing network elements includes receiving at a network element a time synchronization message sent from a master clock element. The network element includes an internal clo... | 04/01/2008 |
| 7352836 | System and method of cross-clock domain rate matching Described are a system and method for providing an interface to synchronize data transfers across clock domains. A first pulse converter receives a request signal in a first clock domain and converts the request signal into a synchronization signal in a second clock... | 04/01/2008 |
| 7352755 | Network interface card (NIC) with phase lock rise time control generating circuit A Network Interface Card (NIC) for attaching data terminal equipment to a communications network. The NIC includes a Phase Lock Loop (PLL) with a master delay structure that is operatively coupled to at least one delay line structure. The PLL generates control pulse... | 04/01/2008 |
| 7353320 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 04/01/2008 |
| 7352834 | Code phase synchronization The invention relates to a method for synchronizing the phase of a code available at a receiving unit with the phase of a corresponding code of which samples are received at said receiving unit. The synchronization comprises comparing a received code sample with dif... | 04/01/2008 |
| 7349497 | Receiver circuit A receiver circuit is for processing a received signal which includes at least a first portion and a second portion which repeats the content of the first portion after a repeat interval. For example, the receiver may be for DVB-T signals using COFDM. In order to en... | 03/25/2008 |
| 7350092 | Data synchronization arrangement A data synchronization arrangement is provided for exchanging clocked data between different clock domains running at the same clock frequency but at an arbitrary relative phase shift. An input data stream synchronized in the first clock domain is written into respe... | 03/25/2008 |
| 7350002 | Round-robin bus protocol A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the dev... | 03/25/2008 |
| 7349409 | Receiver for the recovery of the clock in the transport of CBR services, originating both from DCTI transmitters and from SRTS transmitters A receiver provides for the recovery of the clock in the transport of CBR services originating both from DCTI transmitters and from SRTS transmitters over an ATM network, and comprises a generator of the control parameter, an oscillation system, a DCTI generator, a ... | 03/25/2008 |
| 7349458 | Linear receivers for time-hopping impulse radio systems In a time-hopped impulse radio system, each symbol is transmitted over a channel having different multipath components as a set of Nf frames. Each frame includes one pulse. All frames of a received signal corresponding to the symbol are sampled to generat... | 03/25/2008 |
| 7349269 | Programmable DQS preamble A method and apparatus for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted specifically for enabling the data strobe preamble. At least one of the bi... | 03/25/2008 |
| 7349432 | Methods for changing the bandwidth of a circuit switched channel The present invention relates to methods for changing the bandwidth of a circuit switched channel in a time division multiplexed network, wherein said channel comprises a set of time slots within each recurring frame of a bitstream between a first node and a second ... | 03/25/2008 |
| 7346135 | Compensation for residual frequency offset, phase noise and sampling phase offset in wireless networks Improved performance, particularly gain in SNR, in high-bandwidth OFDM receivers, software and systems is achieved by compensating channel estimates not only for carrier frequency offset and phase noise, but also for interference caused by sample phase jitter. At hi... | 03/18/2008 |
| 7346138 | Method of operating a message receiver A method of operating a message receiver for a message, that is present as a burst, which includes at least a training sequence and useful data is performed by stepwise synchronizing the receiver with the burst as the burst is received. ... | 03/18/2008 |
| 7342944 | Method and apparatus for decoding a coded digital audio signal which is arranged in frames containing headers With audio data reduction on the basis of ISO/IEC standard 11172-3, a frame length varying by 8 bits is used at a sampling frequency of 44.1 kHz in order to arrive, on average, at a particular fixed data rate. The lengthening of a data frame is signalled by a paddin... | 03/11/2008 |
| 7342972 | Timing synchronization using dirty templates in ultra wideband (UWB) communications Techniques are described for synchronizing the timing of the receiver with the received waveform in ultra wideband (UWB) communication systems. The described techniques correlate the received waveform with dirty templates, i.e. segments of the received waveform, wit... | 03/11/2008 |
| 7342984 | Counting clock cycles over the duration of a first character and using a remainder value to determine when to sample a bit of a second character In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock. The number of cycles counted is then divided by the number of bits cou... | 03/11/2008 |
| 7343255 | Dual source real time clock synchronization system and method A dual source real time clock (RTC) synchronization system and method for implementation within automatic meter reading (AMR) systems that provide system-wide device time synchronization. In one embodiment, a microcontroller-implemented RTC counts elapsed seconds fr... | 03/11/2008 |
| 7342953 | Synchronization detection circuit A synchronization detection circuit includes: a matched filter 105 for outputting a correlation value, between a spreading code and data that is obtained by sampling a code spread signal 101, using a sampling clock for one chip cycle; a sampling clock ... | 03/11/2008 |
| 7339977 | Signal strength assisted searcher and acquisition A code division, multiple access (CDMA) receiver includes an RF section for receiving a CDMA signal through a channel; a circuit for determining an instantaneous total received power (Io) of the received CDMA signal; and a searcher that is one of enabled for operati... | 03/04/2008 |
| 7340631 | Drift-tolerant sync pulse circuit in a sync pulse generator A drift-tolerant sync generation circuit and sync generation method for a sync pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock do... | 03/04/2008 |
| 7340021 | Dynamic phase alignment and clock recovery circuitry A dynamic phase alignment circuit is provided that aligns data signals to a phase of a forwarded clock at each channel in a multi-channel communications protocol. A forwarded clock is sent to a phase locked loop (PLL) circuit that generates multiple clock phases of ... | 03/04/2008 |
| 7340736 | Electronic device with an update agent that employs preprocessing techniques for update Methods of updating an electronic device having an update agent employing preprocessing techniques is disclosed. The methods described permit an electronic device having a non-volatile memory to update a plurality banks in an efficient manner, by preprocessing the o... | 03/04/2008 |
| 7339981 | Shifted training sequences in a communications system Embodiments of the present invention can be used to select a training sequence used by a base station and a user terminal for communications. In one embodiment, selecting the training sequence to use includes first selecting a training sequence from a set of trainin... | 03/04/2008 |
| 7340022 | Method, a sender, a receiver, an optical network element and a serialized packet format for transmitting packets The present invention relates to a method for transmitting packets comprising a synchronization part (sync′) and a payload part (dat1, dat2), wherein the transmission format comprises a shortened synchronization part (syn′) and the payload part is ... | 03/04/2008 |
| 7339985 | Zero crossing method of symbol rate and timing estimation System and method for analyzing communication signals. A digital signal comprising multiple samples is received, representing a plurality of binary symbols. Zero crossings of the signal are determined, each comprising a respective first sample immediately preceding ... | 03/04/2008 |
| 7340023 | Auto baud system and method and single pin communication interface In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock. The number of cycles counted is then divided by the number of bits cou... | 03/04/2008 |
| 7339948 | Industrial controller providing deterministic communication on ethernet A transmission schedule is overlaid on the Ethernet protocol to allow use of this readily available high speed protocol for transmission of I/O data communicated in an industrial control environment and requiring a high degree of determinism. Scheduling improves loa... | 03/04/2008 |
| 7339853 | Time stamping events for fractions of a clock cycle Generally, the embodiments are directed to circuits and methods for time stamping an event at a fraction of a clock cycle. A time stamping circuit comprises two or more detection circuits. The detection circuits receive an event-in signal and generate event signals ... | 03/04/2008 |
| 7339955 | TDMA communication method and apparatus using cyclic spreading codes Systems and methods of ultra-wideband communication are provided. In one embodiment, an ultra-wideband communication system divides a stream of data conveying symbols into a plurality of unspread substreams. A common spreading code is generated at the ultra-wideband... | 03/04/2008 |
| 7340630 | Multiprocessor system with interactive synchronization of local clocks A multiprocessor computer system comprises multiple data processors, each with an internal clock for providing time stamps to application software. The processors take turns as synchronization masters. The present master transmits a “request” time stamp (indicat... | 03/04/2008 |
