Did You Know...
...that two musicians were responsible for the invention of color print film? Fascinated by photography, Leopold Godowsky and Leopold Mannes worked together to produce an easy-to-use, practical color film. They worked full time as music teachers and gave concerts while experimenting during their off hours in Mannes' kitchen. Their success earned them full-time, well-paying jobs at Kodak and their efforts resulted in Kodachrome film, which was introduced in 1935.
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| Number | Title | Issue Date |
| 7596196 | Timing recovery in error recovery for iterative detection A decoding system includes a timing loop for use in error recovery mode operations, in which “fast decode” bit values that are used for timing recovery purposes in the normal modes of operation are replaced, at an appropriate iteration in the error recovery mode... | 09/29/2009 |
| 7593495 | Method for performing high resolution phase alignment of multiple clocks using low resolution converters The offset between a reference clock output signal and a target clock output signal are measured during a predetermined period. Based on the measurement, an offset signal is generated. The offset signal is integrated into an average offset signal value, wherein the ... | 09/22/2009 |
| 7590207 | Modular serial interface in programmable logic device A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably configured as a loop circuit (e.g., a phase-locked loop). This is accom... | 09/15/2009 |
| 7590208 | Circuit and method for generating a timing signal, and signal transmission system performing for high-speed signal transmission and reception between LSIs A signal transmission system has a plurality of signal lines, a plurality of transmitting circuits, a plurality of receiving circuits, and a timing adjusting circuit. The transmitting circuits are provided for the signal lines. Each of the receiving circuits receive... | 09/15/2009 |
| 7587013 | Apparatus for updating gain of loop filter For updating a gain of a loop filter from a timing error signal, a timing signal estimator generates a current timing signal estimation value from a prior timing error estimation value, a prior gain value, and a prior timing signal estimation value. A timing error e... | 09/08/2009 |
| 7587012 | Dual loop clock recovery circuit A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which gene... | 09/08/2009 |
| 7587011 | Digital-data receiver synchronization method and apparatus Digital data receiver synchronization is provided with composite phase-frequency detectors, mutually cross-connected comparison feedback or both to provide robust reception of digital data signals. A single master clock can be used to provide frequency signals. Adva... | 09/08/2009 |
| 7580491 | Quarter-rate clock recovery circuit and clock recovering method using the same A quarter-rate clock recovery circuit includes a clock generator, a phase interpolation unit, a phase detector, and a controller. The clock generator generates first through fourth clocks having a quarter frequency of a data-rate of input data, the second, third and... | 08/25/2009 |
| 7564935 | AGC circuit which is hard to be influenced by level of input signal Provided is an AGC circuit which is hard to be influenced by the level of an input signal. The AGC circuit includes an amplification element 11 which has an input terminal 11g for receiving an input signal Vin, a ground terminal 11... | 07/21/2009 |
| 7564934 | Digital signal processing of multi-sampled phase The DSP MSP invention provides an implementation of programmable algorithms for analyzing a very wide range of low and high frequency wave-forms. The DSP MSP comprises a synchronous sequential processor (SSP) for real time capturing and processing of in-coming wave-... | 07/21/2009 |
| 7555084 | System and method of digital system performance enhancement The present invention performs a digital computation with a lower than worst-case-required clock period (i.e., a faster clock), and at the same time performs the same computation with a larger, worst-case-assumed, clock period (i.e., a slower clock) on a second syst... | 06/30/2009 |
| 7555085 | CDR algorithms for improved high speed IO performance A data receiver system. The system includes a clock generator configured to output a reference clock and circuitry configured to measure a direction of a phase difference between an input data stream and the reference clock. The circuitry is further configured to in... | 06/30/2009 |
| 7555086 | Plural circuit selection using role reversing control inputs Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or sync... | 06/30/2009 |
| 7555083 | Synchronizing circuit for stably generating an output signal The present invention relates to a synchronizing circuit for stably generating an output signal irrespective of the frequency difference of clocks. According to the present invention, the synchronizing circuit receives an input signal synchronized with a first clock... | 06/30/2009 |
| 7551702 | Method and circuit arrangement for synchronizing a function unit with a predetermined clock frequency A receiver is synchronized with a first clock frequency or signal of a transmitter for the proper reception of transmitted and received signals, such as data carrying signals (DS). The first clock frequency is for example a carrier frequency. A local oscillator gene... | 06/23/2009 |
| 7545895 | High performance W-CDMA slot synchronisation for initial cell search with reduced hardware Two preferred embodiments provide slot synchronization of an initial cell search. Two Finite Impulse Response (FIR) filters are used to correlate the synchronization codes transmitted in the downlink (forward link). A sign bit is taken after the first FIR to signifi... | 06/09/2009 |
| 7545896 | Asynchronous multi-clock system A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of ... | 06/09/2009 |
| 7545897 | Method and apparatus for recording time information for digital data streams A recording medium, an apparatus and a method for recording time information of digital data streams are provided. The apparatus in one embodiment includes a time information creating unit creating a first time field and a second time field, wherein the first time f... | 06/09/2009 |
| 7542534 | Method and an apparatus to reduce electromagnetic interference A method and an apparatus to reduce electromagnetic interference (EMI) have been presented. In one embodiment, the method includes using a first clock signal to create a second clock signal having a fundamental frequency lower than a frequency of the first clock sig... | 06/02/2009 |
| 7542532 | Data transmission device and input/output interface circuit A clock generator supplies a clock signal to a data transmission circuit for a jitter resistance test of a data transmission/reception circuit, while supplying a clock signal to a data reception circuit. At this time, the clock signal supplied by the clock generator... | 06/02/2009 |
| 7542533 | Apparatus and method for calibrating the frequency of a clock and data recovery circuit Embodiments of the invention include an apparatus and method for continuously calibrating the frequency of a clock and data recovery (CDR) circuit. The apparatus includes a delay arrangement that generates a gating signal, and a gated voltage-controlled oscillator t... | 06/02/2009 |
| 7535981 | Clock generation circuit and method thereof The present invention generates an output clock signal CLKreq having a frequency freq between the frequency fref/A of a divided clock signal CKL1 and the frequency fref/(A+1) of a divided clock signal CLK2. A clock divider circuit selectively generates... | 05/19/2009 |
| 7529329 | Circuit for adaptive sampling edge position control and a method therefor A clock and data recovery circuit (CDR) for receiving high-speed digital data, and having an analog phase offset control capability, is improved by providing an adaptive sampling edge position control. A differential circuit samples the raw data signal at three clos... | 05/05/2009 |
| 7522684 | Signal transmission system For signals to be transmitted through a signal transmission path constituted by a relay device group for relay for each set of a plurality of channels, a timing adjustment unit is provided in both or one of a receiver-side LSI and a transmitter-side LSI for each set... | 04/21/2009 |
| 7522685 | Resynchronizing timing sync pulses in a synchronizing RF system A synchronizing method and system between a Radio Frequency (RF) transmitter and a battery powered receiver wherein the transmitter transmits short duration first periodic sync signals which are used by the receiver to maintain proper synchronization of the receiver... | 04/21/2009 |
| 7515664 | Method of recovering data in asynchronous applications Data is recovered in an asynchronous environment where a sampling clock is generated internally, and is not externally frequency locked, by using programmable delay modules each providing a number of delay tap outputs. To recover data, two of the delay modules are u... | 04/07/2009 |
| RE40695 | Clock phase detecting circuit and clock regenerating circuit each arranged in receiving unit of multiplex radio equipment The present invention relates to a clock phase detecting circuit and a clock regenerating circuit each arranged in a receiving unit of multiplex radio equipment. The receiving unit of the multiplex radio equipment includes an identifying circuit for identifying a si... | 04/07/2009 |
| 7515663 | Method and apparatus for synchronising receivers A receiver produces complex data samples from a demodulated received signal. The data samples, which may form a preamble identifying a wireless LAN data burst, are arranged in a sequence comprising sub-sequences having a predetermined relationship with each other. A... | 04/07/2009 |
| 7515665 | GFSK/GMSK detector with enhanced performance in co-channel interference and AWGN channels A detector for detecting a received signal according to a Gaussian shift keying (“GFSK/GMSK”) modulation scheme. The detector may enhance a detection performance of the receiver while limiting one or more implementation impacts. An implementation impact may incl... | 04/07/2009 |
| 7515666 | Method for dynamically changing the frequency of clock signals A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second ... | 04/07/2009 |
| 7515667 | Method and apparatus for reducing synchronizer shadow In one embodiment, a method for reducing synchronizer shadow involves: 1) receiving and deserializing a serialized data flit of known length, under control of a first clock domain; 2) before receiving all of the serialized data flit, beginning to resolve a valid sig... | 04/07/2009 |
| 7512200 | Circuit to detect clock delay and method thereof Provided are a circuit and a method of detecting clock delay where the circuit to detect clock delay includes a delay detection circuit and a clock forwarding circuit, the delay detection circuit detects a delay between a predetermined output clock signal and an inp... | 03/31/2009 |
| 7496166 | Dual clock spread for low clock emissions with recovery A method and apparatus provides for the generation and recovery of a stable clock signal having harmonic emission suppressions using dual spread spectrum clock signals. The transmission frequencies of non-mixed, spread spectrum lower frequency clock signals may be v... | 02/24/2009 |
| 7492846 | Standard wave receiver and time code decoding method A standard wave receiver and a time code decoding method, which receive a standard wave including a time code signal, in which one frame including plural time codes is repeated, and decode the time codes, are provided. The time code signal is sampled over a period, ... | 02/17/2009 |
| 7489751 | Method and apparatus for synchronization of a receiver to a transmitter In a method for synchronization of a receiver to a transmitter which periodically transmits a sequence which is known in the receiver, a subset of possible synchronization times is determined in a first selection process by repeated correlation of the received signa... | 02/10/2009 |
| 7486753 | Synchronization establishment circuit and synchronization establishment method A terminal is wirelessly connected to a base station. The terminal has a timer and a controller. The timer has a register for storing a beacon interval as a comparison value. The timer also includes a beacon counter for counting timer clocks. The timer also includes... | 02/03/2009 |
| 7486752 | Alignment of clock signal with data signal A received clock signal is aligned (“eye centered”) with a received data signal by recovering a separate clock from the data signal and comparing and aligning the received clock with the recovered clock by delaying one or both of the received clock and the recei... | 02/03/2009 |
| 7480358 | CDR-based clock synthesis A clock signal can be synthesized by performing a clock and data recovery (CDR) operation on a potentially noisy clock source signal which has a known transition density. The CDR operation produces a desired clock signal in response to the clock source signal. In or... | 01/20/2009 |
| 7480357 | System and method for effectuating the transfer of data blocks across a clock boundary A system and method for effectuating the transfer of data blocks having intervals across a clock boundary between a first clock domain and a second clock domain. A first circuit portion provides the data blocks to a second circuit portion. A synchronizer controller ... | 01/20/2009 |
| 7474720 | Clock and data recovery method and digital circuit for the same A clock data recovery circuit has a good jitter tolerance characteristic and a broad data recovery range in the event of a wander, that is, a good wander-tracking characteristic of a recovered clock signal. The clock data recovery circuit executes control to compare... | 01/06/2009 |
