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| Number | Title | Issue Date |
| 7319729 | Asynchronous interface methods and apparatus In a first aspect of the invention, a first method is provided for aligning signals from a first receiver located in a first clock domain to a second receiver located in a second clock domain. The first method includes the steps of creating a programmable delay elem... | 01/15/2008 |
| 7319730 | Data communication method and data communication device and semiconductor device The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method include... | 01/15/2008 |
| 7320043 | Split computer architecture to separate user and processor while retaining original user interface A network interface is described in which a single computer bus is split over a long distance into two or more inter-communicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided.... | 01/15/2008 |
| 7319686 | Frame synchronization in multi-cell systems with a data interface A method of timing in a multi-cell system requiring synchronization of frames in transmission is provided. Transceivers of a wired data interface between a central controller and multiple base stations are synchronized to a frame timing clock up to a difference in p... | 01/15/2008 |
| 7317905 | Radio-controlled clock and method for gaining time information Time signals for controlling a radio clock are transmitted by a transmitter and received by a receiver as amplitude modulated time signals, formed of a multitude of time frames. Each time frame has a constant duration. These time signals are first automatically ampl... | 01/08/2008 |
| 7317773 | Double data rate flip-flop Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are altern... | 01/08/2008 |
| 7317318 | FEXT cancellation of mated RJ45 interconnect A network test instrument provides maximum compensation of FEXT by use of mutual inductance between one or more signals. The inductance is suitably formed as a PCB trace component, or as discrete components. ... | 01/08/2008 |
| 7315539 | Method for handling data between a clock and data recovery circuit and a data processing unit of a telecommunications network node of an asynchronous network, as well as a bit rate adaptation circuit and a clock and data recovery system A method for handling data between a clock and data recovery system CDR and a data processing unit DP of a telecommunications network node TNN of an asynchronous communications network, using a bit rate adaptation circuit BAS, the bit rate adaptation system BAS incl... | 01/01/2008 |
| 7315546 | Alignment of clock domains in packet networks Disclosed is a method and apparatus for aligning clock domains over an asynchronous network between a source controlled by a first clock and a destination controlled by a second clock. The predicted delay is estimated for transmitting packets between a source and de... | 01/01/2008 |
| 7315764 | Integrated circuit, method, and computer program product for recording and reproducing digital data An integrated circuit to control a media player/recorder having a wireless receiver, a storage device, and an output circuit, wherein the wireless receiver receives a signal representing encoded media data, and a method and computer program product for same. It comp... | 01/01/2008 |
| 7315584 | Coherent receiver A coherent receiver receives a set of signals which are spaced in phase, or phase and polarization, and a reference signal. The receiver processes the set of signals to determine which of the set of signals has a predetermined association (e.g. closest in phase) wit... | 01/01/2008 |
| 7315731 | Method of measuring and calibrating frequency down converter A frequency down converter that maintains accuracy even if the frequency pass band is wide uses a reference frequency band within the frequency pass band, the reference frequency band being resistant to degradation by aging or temperature variation. The ideal charac... | 01/01/2008 |
| 7315957 | Method of providing a second clock while changing a first supplied clock frequency then supplying the changed first clock Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selecte... | 01/01/2008 |
| 7315583 | Digital subscriber line (DSL) modems supporting high-speed universal serial bus (USB) interfaces and related methods and computer program products The present invention provides asymmetric digital subscriber line (ADSL) modems including a discrete multitone (DMT) modem module. The DMT modem module includes a digital signal processor (DSP) configured to process control signals for initializing the ADSL modem du... | 01/01/2008 |
| 7313635 | Method and apparatus for simulating a load on an application server in a network A method is disclosed for simulating a load on an application server in a network. The method intercepts data packets of a request from a sender to a receiver. The data packets to be intercepted can be selected according to specified criteria, such as communications... | 12/25/2007 |
| 7313791 | Firmware update network and process employing preprocessing techniques A network for updating firmware, drivers, or application software facilitates the access to generated update packages by electronic devices and the update of firmware, drivers, content or application software in a fault tolerant mode. A “Bubbles” technique is em... | 12/25/2007 |
| 7313204 | Method and device for transmitting and identifying a modulation type in digital communication systems by way of a phase rotation factor applied to a training sequence Data symbols in the training sequence are rotated at the transmitter end through a phase rotation factor which is specific for a given modulation type that is used. For blind modulation detection at the receiver end, the data symbols are derotated through different ... | 12/25/2007 |
| 7313209 | Method and arrangement to synchronize a multi-carrier transmission system The invention relates to a method to synchronise a multi-carrier transmission system wherein a time misalignment between a transmitter and a receiver is determined through an average of at least two pilot tones phase errors (Øi) weighted in accordance wi... | 12/25/2007 |
| 7313187 | High-speed serial linking device with de-emphasis function and the method thereof A high-speed serial linking device with de-emphasis function for receiving a parallel data and accordingly outputting a de-emphasized transmission differential pair. The high-speed serial linking device includes a parallel-to-serial unit, a pre-driver, and an output... | 12/25/2007 |
| 7313210 | System and method for establishing a known timing relationship between two clock signals A system and method for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transpor... | 12/25/2007 |
| 7313179 | Minimizing windowing effects in particular for signal recovery A measured signal, such as a high-speed digital pulse, transmitted through a system is corrected. The measured signal is sampled to a sampled signal sequence, and a signal series is provided as a plurality of the sampled signal sequences put together successively. T... | 12/25/2007 |
| 7313211 | Method and apparatus for phase detection The present invention relates to a method and apparatus for generating an output signal in dependence on a phase difference between two periodic signals. The present invention is particularly useful in phase locked loops and delay locked loops, in which a controllab... | 12/25/2007 |
| 7310057 | Latch clock generation circuit and serial-parallel conversion circuit A serial-parallel conversion circuit in which power consumption is reduced is provided by using a latch clock generation circuit including multiple latch signal generation circuits which outputs a latch signal with a period of an integer multiple of that of a system... | 12/18/2007 |
| 7310396 | Asynchronous FIFO buffer for synchronizing data transfers between clock domains An asynchronous FIFO buffer communicates data between first and second clock domains. The FIFO buffer includes a shift register that accepts and shifts out data at a relatively high output frequency required for the second clock domain. The input data is loaded into... | 12/18/2007 |
| 7310400 | Data recovery device and method A data recovery device. The device adjusts a digital signal according to a pulse signal output by a phase-locked loop circuit. The sampling circuit samples each bit of the digital signal five times to generate a first sampled signal. The data delay buffer decides a ... | 12/18/2007 |
| 7310398 | Symbol synchronizing device A symbol synchronization device that enables effective symbol synchronization establishment and synchronization holding for an arbitrary spread code sequence. The device includes (i) a primary demodulation section for receiving a spread modulation signal where chips... | 12/18/2007 |
| 7310393 | Method and apparatus for synchronization of the OFDM systems A method and apparatus for the signal synchronization of an orthogonal frequency division multiplexing system includes a delay conjugate multiplication module, a phase processor and an edge detector. It provides estimates for the boundaries of inter-symbol interfere... | 12/18/2007 |
| 7310752 | System and method for on-board timing margin testing of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 12/18/2007 |
| 7310748 | Memory hub tester interface and method for use thereof A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command,... | 12/18/2007 |
| 7308064 | Frame synchronization method based on differential correlation information in satellite communication system Provided is a frame synchronization method for synchronizing frames with pilot blocks added thereto based on differential correlation information in a satellite communication system. The method can acquire a highly reliable frame synchronization estimation value by ... | 12/11/2007 |
| 7308063 | Apparatus, and associated method, for effectuating post-FFT correction of fine frequency offset In an orthogonal frequency division multiplexing (OFDM) system, a receiver of an OFDM signal via an air interface defines training symbols to be included in the frame structure of the air interface and a post-FFT receiver algorithm that can efficiently estimate a fr... | 12/11/2007 |
| 7308059 | Synchronization of data links in a multiple link receiver A dual link receiver terminates, recovers, channel aligns, and link aligns a plurality of primary link channels and a plurality of secondary link channels. The plurality of primary link channels and the plurality of secondary link channels are each received, bit rec... | 12/11/2007 |
| 7308025 | Transmitters providing cycle encoded signals In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the en... | 12/11/2007 |
| 7308023 | Dual function clock signal suitable for host control of synchronous and asynchronous target devices A host device in a data communication system provides a dual-function clock/enable signal at a single output port shared by at least one asynchronous target device and at least one synchronous target device. In the asynchronous operating mode, the host device genera... | 12/11/2007 |
| 7305023 | Receivers for cycle encoded signals In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the en... | 12/04/2007 |
| 7302657 | Optimization of the design of a synchronous digital circuit The design of a synchronous digital circuit (1) can be modified. The circuit comprises a number of clocked storage devices (2, 3, 4, 5,) and a number of combinational logic elements defining combinational paths (6, 7, 8, 9,) between at least som... | 11/27/2007 |
| 7301377 | Demodulation apparatus and receiving apparatus A demodulation apparatus that can support various oscillation frequencies. The portable phone device includes a frequency synthesizer for generating a local-oscillation signal having a local oscillation frequency for converting the frequency of an input receiving si... | 11/27/2007 |
| 7298806 | Method and system for data-aided timing offset estimation for frequency selective fading channels The disclosed invention provides a system, a method and a computer program product for timing offset estimation for frequency selective fading channels in wireless communication systems. The disclosed invention first obtains a corrected received signal using the rec... | 11/20/2007 |
| 7295139 | Triggered data generator A triggered data generator reduces timing jitter at the start of serial data output from arrival of a trigger signal. A trigger detecting circuit 8 produces trigger phase information indicating the phase relationship between the trigger signal and a reference... | 11/13/2007 |
| 7295638 | Communication device A direct sequence spread spectrum (DSSS) receiver (100) consistent with certain embodiments has a frequency generator (112) that generates a local oscillator signal without use of a piezoelectric crystal. A frequency converter (108) receives the... | 11/13/2007 |
