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| Number | Title | Issue Date |
| 7450666 | Ask demodulation device and wireless device using the same A delay section delays a detected signal by less than one bit time in the NRZ data. A subtraction section performs subtraction between a delayed signal and the detected signal, and outputs a resultant signal. A clock extraction section extracts, from crossing points... | 11/11/2008 |
| 7359471 | Data communication method and data communication device and semiconductor device The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method include... | 04/15/2008 |
| 7343255 | Dual source real time clock synchronization system and method A dual source real time clock (RTC) synchronization system and method for implementation within automatic meter reading (AMR) systems that provide system-wide device time synchronization. In one embodiment, a microcontroller-implemented RTC counts elapsed seconds fr... | 03/11/2008 |
| 7319722 | Circuit for the decoding of biphase signals A decoding circuit and associated method are provided for decoding a biphase signal. The decoding circuit may include a precharging register to precharge a pair of states of the biphase signal, where a state of the pair of states is precharged at each pulse of a per... | 01/15/2008 |
| 7319730 | Data communication method and data communication device and semiconductor device The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method include... | 01/15/2008 |
| 7295601 | Method and apparatus for performing digital timing recovery on oversampled 802.11b baseband signals An apparatus and method for performing digital timing recovery includes a rotating demultiplexor receiving a four times oversampled baseband signal and providing four downsampled phases at respective outputs. Each output is processed by a correlation detector which ... | 11/13/2007 |
| 7292655 | Apparatus and method and decoding biphase signals A technique of decoding a biphase signal comprises sampling the biphase signal to obtain phase sample values and sampling the biphase signal to obtain magnitude sample values. A first digital signal is derived from the phase sample values and associated bit combinat... | 11/06/2007 |
| 7289589 | Maximum likelihood bit synchronizer and data detector A bit synchronizer (16) that includes a tapped delay line (38) connected to a plurality of timing hypothesis circuits. A control and adjudication circuit (50) is connected to the timing hypothesis circuits, and compares outputs of the timing hyp... | 10/30/2007 |
| 7236153 | Signal production circuit and display device using the same A serial-to-parallel converter circuit is constructed of a plurality of D flip-flops receiving, as a clock signal, data in a single signal of serial data stored in a ROM. Each D flip-flop transmits “high” data to a next stage through a latch operation every time... | 06/26/2007 |
| 7206146 | Biphase magnetic pattern detector using multiple matched filters for hard disk drive A hard disk drive (HDD) holds data using a biphase scheme. A plurality of matched filters are used to detect binary data represented by the biphase pattern without the need for synchronous sampling or equalization. ... | 04/17/2007 |
| 7161992 | Transition encoded dynamic bus circuit A transition encoded dynamic bus includes an encoder circuit at the input to the bus and a decoder circuit at the output to the bus. The encoder circuit generates a signal indicative of a transition at the input to the bus rather than the actual value at the input. ... | 01/09/2007 |
| 7133482 | Decoding method and Manchester decoder A method and a corresponding decoder for decoding a Manchester encoded binary data signal includes receiving the Manchester encoded binary data signal having a first sequence of central bit transitions and a second sequence of initial bit transitions. A local clock ... | 11/07/2006 |
| 7099423 | Method and circuit arrangement for detecting synchronization patterns in a receiver Radio frequency receivers are implemented in a variety of embodiments. In one such embodiment, a radio frequency receiver is implemented for detecting synchronization patterns in a receiver, particularly in a UHF receiver or a VHF receiver, by which the average curr... | 08/29/2006 |
| 7095807 | Method for decoding biphase signals A technique of decoding erroneous biphase signals is disclosed comprising the following steps. First, phase and magnitude sample values (ps, bs) are formed, from which a first digital signal (d1) is derived. From this, associated bit combinations (St1,... | 08/22/2006 |
| 7054361 | Method and apparatus for enhancing an infrared signal protocol An apparatus and method for providing control signals, comprising a processor coupled to a memory, for generating a signal sequence. The processor encodes the signal sequence into a plurality of symbols using a 5 pulse position modulated (5 PPM) scheme. Advantageous... | 05/30/2006 |
| 7050775 | Method and apparatus for securely enabling a radio communication unit from standby mode A radio communication unit employs passive devices and a loop filter to receive a coded frequency modulated wakeup or synchronization signal that enables the receiving radio unit and initiates communications. The loop filter simultaneously tracks phase and frequency... | 05/23/2006 |
| H2155 | Downconvert and average identification of biphase coded signal carrier An improved apparatus and method for determining the carrier frequency in a biphase coded signal such as the course acquisition code signal in a global position sensing system. The described system may also be used for other purposes. The described system is based o... | 05/02/2006 |
| 6999827 | Auto-detection of audio input formats Auto-detection of audio formats is provided by using an auto-detect element to exploit differences among multiple formats to output a format select signal corresponding to the input to the auto-detect element. In a preferred embodiment, edge detection circuitry and ... | 02/14/2006 |
| 6996010 | Fast-sensing amplifier for flash memory A fast-sensing amplifier for a flash memory comprised of a plurality of floating-gate memory devices and having a column line selectively coupled to the devices is disclosed. The column line is quickly discharged to ground before a read-biasing and amplifying circui... | 02/07/2006 |
| 6981166 | Method, apparatus, and computer program product for pacing clocked operations In one aspect, a method for performing clocked operations in a device includes performing, in a device, first and second operations responsive to a clock having a primary frequency f. The device is capable of performing the operations within X and Y cycles of the cl... | 12/27/2005 |
| 6981204 | Programmable glitch filter for an asynchronous data communication interface An apparatus and a method for filtering glitches in a data communications controller receiving asynchronous input data signals varying between two signal levels representing two bit values and having a predetermined input bit period, and sending output data signals ... | 12/27/2005 |
| 6977973 | System and method for decoding manchester data A method for decoding Manchester data is provided that includes receiving input data comprising at least two transition types. Each transition of a specified transition type in the input data is detected. For each pair of consecutive transitions of the specified tra... | 12/20/2005 |
| 6952399 | Method and apparatus for synchronizing the coding and decoding of information in an integrated services hub A method and system for extrapolating a sampling rate from received digital cells in an integrated services hub in residential or business telecommunication systems. The system is implemented by a CPU controlling the hub operations. An input buffer is implemented by... | 10/04/2005 |
| 6914822 | Read-biasing and amplifying system A fast-sensing amplifier for a flash memory comprised of a plurality of floating-gate memory devices and having a column line selectively coupled to the devices is disclosed. The column line is quickly discharged to ground before a read-biasing and amplifying circui... | 07/05/2005 |
| 6904539 | Method of determining data transfer speed in data transfer apparatus A method of determining a transfer speed of an encoded data signal including a clock signal and a data signal is provided. First, the encoded data signal is decoded to generate a decoded clock signal. Then, a data transfer speed of the encoded data signal is determi... | 06/07/2005 |
| 6782300 | Circuits and methods for extracting a clock from a biphase encoded bit stream and systems using the same A method of extracting a clock from a biphase encoded bit stream includes the step of detecting a stream of samples each having a sample size measured between consecutive bit phase transitions. A sample length is determined for each sample, the sample length approxi... | 08/24/2004 |
| 6768433 | Method and system for decoding biphase-mark encoded data A method and system for decoding a biphase-mark input stream is disclosed. Aspects of the present invention include receiving an external biphase-mark input stream by a receiver module; recovering timing information from the input stream; decoding the input stream t... | 07/27/2004 |
| 6757341 | Digital audio interface signal demodulating device In a digital audio interface signal demodulating apparatus (DDAp) that adds a preamble (PA) and additional information (V, U, C, P) to a digital audio signal (Sda) and demodulates into a digital audio interface signal (Sdai) after subjected to bi-phase modulation fo... | 06/29/2004 |
| 6628212 | State-driven over-sampling manchester decoder A method and apparatus for a state-driven decoder for decoding a Manchester encoded signal. The decoder comprises an input sampling stage, an over-sampling clock, and a digital logic state machine. The over-sampling clock operates at a frequency which is ... | 09/30/2003 |
| 6549596 | Fully digital phase aligner A fully digital phase aligner includes a control loop acting upon a delay line comprising at least a cascade of delay cells, each cell being individually configurable to produce one of two selectable propagation delays as a function of the logic state of ... | 04/15/2003 |
| 6539071 | Frequency correction at the receiver end in a packet transmission system The invention relates to a system for transmitting packets from interactive terminals to a head station. The terminals intended for consumers are provided with local oscillators which are not very accurate and use carriers having frequency errors which ar... | 03/25/2003 |
| 6449315 | Serial line synchronization method and apparatus Apparatus, and an accompanying method, for transmitting a frame synchronization signal and a data signal simultaneously through a serial transmission medium (170). Specifically within a data transmitter (105), a frame synchronization signal, a clock signa... | 09/10/2002 |
| 6388717 | Digital television transmitting system having data and clock recovering circuit A digital television transmitting system is presented having a recovery circuit for recovering non-return to zero (NRZ) data pulses and transport clock pulses from a biphase-mark serial data pulse stream and wherein the recovered NRZ data pulses and the r... | 05/14/2002 |
| 6275679 | Secure communication using array transmitter The radio transmission circuit comprises 16 antenna elements in a broadside array. A carrier wave is routed to the 16 elements and the phase to each element is adjusted to direct the transmitted wavefront toward a selected receive point. Prior to transmis... | 08/14/2001 |
| 6249555 | Low jitter digital extraction of data from serial bitstreams A low jitter method for extracting clock or data from a serial digital bitstream generates from a digital decoder a window signal from the serial digital bitstream by sampling the serial digital bitstream with a sample clock signal. The window signal enve... | 06/19/2001 |
| 6249558 | Method for transmitting digital data impulses Before digital data impulses are transmitted from a transmitter to a receiver that includes a data acquisition signal generator, at least one synchronizing impulse (syn1, . . . ) is transmitted for synchronizing the transmitter with the receiver with rega... | 06/19/2001 |
| 6236687 | Decision directed phase locked loop (DD-PLL) for use with short block codes in digital communication systems An improved digital decision directed phase locked loop (DD-PLL) for use with short block codes using phase shifting keying (PSK) modulation. The improvement involves a conventional digital phase lock loop which is modified to base its loop corrections on... | 05/22/2001 |
| 6204725 | Circuit for demodulating digital signal undergoing different modulation schemes A circuit for demodulating a signal having a temporal mixture of different modulation schemes applied thereto includes a synchronization-word-detection unit which detects synchronization words included in the signal, and generates first and second positio... | 03/20/2001 |
| 6201837 | Apparatus for receiving broadcasting signals An apparatus for receiving broadcasting signals, which includes a tuner for receiving a digital audio broadcasting signal, a channel decoder for obtaining audio information data, service information data and control information based on the digital audio ... | 03/13/2001 |
| 6128112 | Weighted-sum processing method and apparatus for decoding digital signals The method and associated apparatus of the present invention decodes digital signals by appropriately weighting the respective noise portions of the two phase segments generated by the detector, such as an APD in an optical communications system, such tha... | 10/03/2000 |
