Quotables
"That’s an amazing invention, but who would ever want to use one of them?"
President Rutherford B. Hayes ; Said in 1876, after Alexander Graham Bell demonstrated the telephone to him at the White House
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6587521 | Signal estimator and program stored memory medium A signal estimator is provided that can track a large frequency offset. A received signal distorted in a transmission path is phase-rotated by the phase rotator (102) and is then estimated by the maximum likelihood sequence estimator (MLSE) (103). The pha... | 07/01/2003 |
| 6580765 | Apparatus for recovering symbol timing in cap-based high-speed communication system using single-sided prefilter pair An apparatus for recovering symbol timing in a CAP-based high-speed communication system such as an ADSL or VDSL, using a single-sided prefilter pair, in which timing information is obtained by means of the single-sided prefilter pair and a multiplier ins... | 06/17/2003 |
| 6577685 | Programmable digital signal processor for demodulating digital television signals A phase-lock loop circuit in a demodulator includes a timing recovery block and a carrier recovery block. The demodulator for demodulates a digital signal including symbols. The phase-lock loop includes an integrator processing a block of N samples to pro... | 06/10/2003 |
| 6574288 | Method and apparatus for adjusting a digital control word to tune synthesized high-frequency signals for wireless communications A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loo... | 06/03/2003 |
| 6574287 | Frequency/Phase comparison circuit with gated reference and signal inputs Disclosed is a frequency-locked loop (FLL), which attempts to bring about frequency and phase synchronization between two signals over the control bandwidth of the loop: a reference signal and a voltage-controlled oscillator (VCO) signal. For example, the... | 06/03/2003 |
| 6567479 | System and method for extracting and compensating for reference frequency error in a communications system A system for extracting and compensating for reference frequency error adapted for use with a communication system. The system includes a frequency generator for outputting a reference signal of a first frequency. The frequency generator has acontrol inpu... | 05/20/2003 |
| 6559892 | Video signal transmitter To provide a video signal transmission apparatus capable of correctly transmitting a digital video signal. A PLL circuit 5 has a first cutoff frequency lower than the frequency of a horizontal synchronization signal contained in a digital video signal S9.... | 05/06/2003 |
| 6556591 | Method and apparatus for upstream burst transmission synchronization in cable modems A system for synchronizing the upstream burst transmission in a cable system to a time specified by the cable head end is disclosed. The system includes a free running counter within a cable modem (CM) or network interface unit (NIU), along with logic to ... | 04/29/2003 |
| 6553040 | Method and apparatus for upstream burst transmission synchronization in cable modems A system for synchronizing the upstream burst transmission in a cable system to a time specified by the cable head end is disclosed. The system includes a free running counter within a cable modem (CM) or network interface unit (NIU), along with logic to ... | 04/22/2003 |
| 6549596 | Fully digital phase aligner A fully digital phase aligner includes a control loop acting upon a delay line comprising at least a cascade of delay cells, each cell being individually configurable to produce one of two selectable propagation delays as a function of the logic state of ... | 04/15/2003 |
| 6546059 | Adaptive integrated PLL loop filter A loop filter in the phase-locked loop includes a capacitor having a specific capacitance value. The loop filter also includes an amplifier coupled to a node of the capacitor. The amplifier amplifies a signal at the node in a way that increases the equiva... | 04/08/2003 |
| 6545532 | Timing recovery circuit in a QAM demodulator A timing recovery circuit in a QAM demodulator which uses a symbol rate continuously adaptive interpolation filter. The method of interpolation used in the present invention is defined as a function of time per interpolation interval, rather than as a fun... | 04/08/2003 |
| 6510185 | Single chip CMOS transmitter/receiver A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention includes an antenna for receiving transmitting RF signals, a PLL for generating multi... | 01/21/2003 |
| 6493409 | Phase detectors in carrier recovery for offset QAM and VSB Improved carrier recovery, symbol timing, and carrier phase tracking systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system are disclosed. Carrier and phase recovery systems operate on complex signals representing symb... | 12/10/2002 |
| 6486742 | Blind coherent combiner and method using coupled phase-lock loops Coherent combining apparatus and methods that do not require training to adapt combining weights. The approach employed in the present invention uses phase-lock loops to demodulate input signals. The phase-lock loops are coupled so that their outputs are ... | 11/26/2002 |
| 6483553 | TV receiver for digital/analog combined use The combined TV receiver can receive and process an analog broadcasting signal as well as a digital broadcasting signal, and includes a controller determining whether a channel selected by a user is a digital broadcast or an analog broadcast. The controll... | 11/19/2002 |
| 6473470 | Phase-locked loop circuits for communication system In a phase-locked loop circuit with a signal estimator such as MLSE or DDFSE for correctly detecting and correcting a phase deviation, the phase deviation is held within a predetermined value by amplitude limiting a phase deviation signal obtained from a ... | 10/29/2002 |
| 6466630 | Symbol synchronization in a continuous phase modulation communications receiver Symbol synchronization in a continuous phase modulation receiver is achieved by calculating an arctangent function of a digital sample of the output of a quadrature demodulator. This signal is sampled by integration techniques or filtered to produce signa... | 10/15/2002 |
| 6466270 | Phase locked loop circuit and method of controlling jitter of OSD characters The phase locked loop circuit according to the present invention is configured such that the CPU changes the time constant of the variable LPF filter to an optimum value in accordance with the state of the external signal fed from outside, for example by ... | 10/15/2002 |
| 6466086 | Quadrature demodulator with phase-locked loop A quadrature demodulator applicable to digital communication and digital broadcast is provided, which simplifies the circuit configuration of a quadrature demodulator section and which reduces the labor or man-hours and the time required for adjusting the... | 10/15/2002 |
| 6433830 | Off-air phase lock technique The proposed phase lock technique uses various feedback loops to lock the frequency and phase of a CATV modulator output signal to that of an off-air signal without directly measuring the output frequency. One embodiment includes a tuner for receiving the... | 08/13/2002 |
| 6415004 | Phase detector, timing recovery device using the same, and a demodulator using the timing recovery device In the present invention, the amplitude subtracting type of phase detector of the timing recovery section outputs a difference γi of a synthesized amplitude deviation at 1/2 of a symbol time. The averaging section computes an average value of ... | 07/02/2002 |
| 6411665 | Phase locked loop clock extraction A clock recovery circuit includes a phase locked loop in which the control voltage of a voltage controlled oscillator is controlled by a loop filter driven by the output of a phase comparator. During acquisition of the phase locked condition, a frequency ... | 06/25/2002 |
| 6411660 | Device for reducing lock-up time of Frequency synthesizer A device for reducing a lock-up time in a digital cordless telephone. The telephone includes a first frequency synthesizer for generating a reference frequency, a receiver having a first mixer for mixing the reference frequency with an input frequency to ... | 06/25/2002 |
| 6411658 | Demodulation device A demodulation device having a demodulating circuit that conducts the primary demodulation of received modulation wave, and a carrier recovery circuit that regenerates a carrier from demodulation signal by the demodulating circuit and conducts the seconda... | 06/25/2002 |
| 6404825 | Digital radio receiver lock detector A digital radio tuner lock detector receives an in-phase (I) data signal and a quadrature (Q) data signal. The lock detector processes these signals to compute a data signal power estimate and integrates the data signal power estimate to provide a thresho... | 06/11/2002 |
| 6393073 | Method of frequency offset estimation and correction for adaptive antennas A method of frequency offset estimation and correction for adaptive antennas comprises receiving in a processor samples of a data set having a training data sample sequence. A batch least squares weight solution is computed for the training data sample se... | 05/21/2002 |
| 6389548 | Pulse run-length measurement for HF data signal by dividing accumulated phase difference between first and second zero-crossings by single-cycle range using multiple cycle range sawtooth waveform A system and method for accurately measuring a pulse run length in a high frequency (HF) data signal while utilizing a low analog-to-digital conversion (ADC) sampling rate. Four bits are added to the most significant end of an oscillator's accumulator reg... | 05/14/2002 |
| 6385262 | Method and apparatus for changing the channel bandwidth that is receivable in a radio receiver The present invention relates to an arrangement (1) and a method in a receiver in a multi-mode mobile radio (m), wherein the intention is to design the receiver so that it uses the same hardware to process several different channel bandwidths correspondin... | 05/07/2002 |
| 6370188 | Phase and frequency offset compensation in a telecommunications receiver A modem (55) including receive circuitry (30) implemented by way of a digital signal processor (32, 32') is disclosed. The receive circuitry (30) operates according to a receive clock (CLK.sub.r) that is based upon the output of a free run oscillator (50)... | 04/09/2002 |
| 6366574 | Method and device for recovering synchronization on a signal transmitted to a mobile-telephone receiver Device for recovering synchronization on a signal transmitted to a mobile-telephone receiver, including phase-estimator means (47, 49) for the absolute value (ABS) and the sign (SIGN) of the transmitted signal, estimation processor (64) for processing the... | 04/02/2002 |
| 6356612 | Clock signal reproducing apparatus Analog-to-digital converter 8 samples demodulated data signal 110 inputted from input terminal 14 in synchronism with clock signal 12 and converts the demodulated data signal into digital signal 9. Signal variation direction detection circuit 6 detects wh... | 03/12/2002 |
| 6356599 | AFC device and method of controlling reception frequency in a dual-mode terminal An AFC (Automatic Frequency Control) device and a method of controlling reception frequency in a dual-mode terminal. When a dual-mode terminal uses one or two AFC devices, the time required for acquiring tracking synchronization in a PLL circuit for a fir... | 03/12/2002 |
| 6345173 | Frequency modulator A frequency modulator (50, 150) for modulating a carrier signal according to a modulation data signal to provide a modulated output signal (RFout), comprises a reference signal generator (54, 154) coupled to receive the modulation data signal for performi... | 02/05/2002 |
| 6345079 | Clock signal generation apparatus A clock signal generation apparatus includes a first device for extracting reference information from an input digital signal. An oscillator operates for generating a reference clock signal having a frequency depending on a control signal. A second device... | 02/05/2002 |
| 6339623 | Reference carrier generator device for pulling a reference carrier out of a false stabilized point into a correct stabilized point of synchronism A reference carrier generator device includes a phase error detection unit which detects a phase error between a reference carrier and a carrier of a quadrature modulated wave and outputs a phase error signal indicating the phase error. A loop filter pass... | 01/15/2002 |
| 6337886 | Bit rate-selective type optical receiver, optical regenerative repeater and automatic bit rate discriminating method A receiving apparatus includes a counter for counting for a prescribed period of time the number of bits having one of two different levels, out of bits forming a digital signal which is entered and having the two different levels, and supplying a count s... | 01/08/2002 |
| 6335952 | Single chip CMOS transmitter/receiver A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention includes an antenna for receiving transmitting RF signals, a PLL for generating multi... | 01/01/2002 |
| 6331999 | Serial data transceiver architecture and test method for measuring the amount of jitter within a serial data stream A serial data transceiver architecture and test method are presented for measuring the amount of jitter within a serial data stream. A transmitter of the transceiver receives parallel input data at a transmit data input port, converts the parallel input d... | 12/18/2001 |
| 6330036 | Digital video receiving apparatus The present invention provides a digital video receiving apparatus for displaying a plurality of digital TV pictures on a plurality of receiving terminal apparatuses. The digital video receiving apparatus includes a tuner for extracting the received digit... | 12/11/2001 |
