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| Number | Title | Issue Date |
| 8165247 | Unfolded decision-directed loop, architectures, apparatuses and systems including the same, and methods, algorithms and software for reducing latency in decision-directed loops Unfolded adaptive/decision-directed loops and correction circuits therefor, architectures, apparatuses and systems including the same, and methods, algorithms and software for reducing latency in an adaptive and/or decision-directed loop. Disclosed embodiments advan... | 04/24/2012 |
| 8155240 | Receiver circuit, application of a first and a second proportional element of a digital PLL structure, and method for receiving a frequency-shift keyed signal A receiver circuit, application of a first proportional element and a second proportional element of a digital PLL structure, and method for receiving a frequency-shift keyed signal are provided. A phase signal is calculated from an in-phase signal and a quadrature ... | 04/10/2012 |
| 8111785 | Auto frequency acquisition maintenance in a clock and data recovery device A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input commu... | 02/07/2012 |
| 8094754 | Frequency hold mechanism in a clock and data recovery device A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a fir... | 01/10/2012 |
| 7899137 | Mobile communication system with integrated GPS receiver A Global Positioning System (GPS) receiver integrated with a cellular phone system, comprising a single-balanced mixer, a poly phase filter, a channel select filter, an analog-to-digital converter, a reference frequency source, and a PLL unit is disclosed. The singl... | 03/01/2011 |
| 7826563 | High speed multi-modulus prescalar divider A system and method are provided for multi-modulus division. The method accepts an input first signal having a first frequency and divides the first frequency by an integral number. A second signal is generated with a plurality of phase outputs, each having a second... | 11/02/2010 |
| 7826564 | Complex digital phase locked loop for use in a demodulator and method of optimal coefficient selection A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a... | 11/02/2010 |
| 7817750 | Radio receiver including a delay-locked loop (DLL) for phase adjustment A method, algorithm, architecture, circuits, and/or systems for using a delay-locked loop (DLL) for phase adjustment in a direct conversion radio receiver are disclosed. In one embodiment, a receiver circuit can include: (i) a voltage-controlled oscillator (VCO) for... | 10/19/2010 |
| 7733987 | Clock signal reproduction device and clock signal reproduction method A phase comparator detects time lag or time lead of the phase of a data signal with respect to a reproduced clock signal from a first digital VCO. A random walk filter measures a difference between number of lags and number of leads, controls the first digital VCO t... | 06/08/2010 |
| 7733986 | Receiver and electronic apparatus A receiver has a receiving unit including a PLL, a mixer, and a filter, and demodulating unit including a frequency error detector for detecting a frequency error in a signal from a filter. The PLL includes a local oscillator for supplying a local oscillation signal... | 06/08/2010 |
| 7733985 | Phase-locked loop circuit with a mixed mode loop filter A phase-locked loop circuit includes a phase and frequency detector receiving a reference signal and an output signal of the phase-locked loop circuit for generating a detected signal representing a frequency or phase difference therebetween. A digital charge pump c... | 06/08/2010 |
| 7660366 | Message synchronization over a stochastic network Methods and apparatus to communicate between a local component and a remote component, where the local component is connected to the remote component using a non-deterministic communication link. A local clock is synchronized with a remote clock to within a maximum ... | 02/09/2010 |
| 7643580 | Signal generator circuit having multiple output frequencies A signal generator circuit includes an oscillator operative to generate a first signal having a first frequency associated therewith, and a phase stepper circuit coupled to the oscillator. The phase stepper circuit is configured to receive a plurality of control sig... | 01/05/2010 |
| 7620126 | Method and apparatus for detecting frequency lock in a system including a frequency synthesizer A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downs... | 11/17/2009 |
| 7590194 | Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by frequency synthesizer An information handling system including a frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and ... | 09/15/2009 |
| 7577215 | Angle demodulation apparatus, local oscillation apparatus, angle demodulation method, local oscillation signal generating method, recording medium and computer data signal An FM modulation signal is mixed with a pair of first local oscillation signals to be converted to a pair of base band signals. The base band signals are respectively mixed a pair of second local oscillation signals. The resultant signals are added together, thereby... | 08/18/2009 |
| 7573955 | Digital phase locked loop for sub-μ technologies A digital phase locked loop has a digitally controlled oscillator for generating an output frequency, a phase detector device for detecting the phase difference between a reference frequency and an output frequency of the oscillator. The phase detector device contai... | 08/11/2009 |
| 7564928 | System and method of frequency synthesis to avoid gaps and VCO pulling in direct broadcast statelite systems A system and method for designing a broadband tuner such that VCO pulling is minimized and gaps in frequency coverage are avoided, while total power consumption is reduced, is disclosed. A broadband spectrum is divided into sub-bands and various multipliers to a loc... | 07/21/2009 |
| 7535976 | Apparatus and method for integration of tuner functions in a digital receiver A receiver to process a RF input signal having a plurality of channels includes a direct down conversion circuit, a demodulation circuit, and a local oscillator circuit. The direct down conversion circuit provides a downconverted signal based on the RF input signal ... | 05/19/2009 |
| 7535977 | Sigma-delta based phase lock loop A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PFD to receive a reference signal and a feedback signal and to output signals based on a comparison of the r... | 05/19/2009 |
| 7508888 | Method and apparatus for precise open loop tuning of reference frequency within a wireless device A communications subsystem for a wireless device for correcting errors in a reference frequency signal. The communications subsystem comprises a frequency generator for generating the reference frequency signal and a closed loop reference frequency correction module... | 03/24/2009 |
| 7505533 | Clock data recovery circuit with phase decision circuit A clock data recovery circuit with feedback type phase discrimination. The clock data recovery circuit has an output signal of B bits and comprises a sampler, a phase region decision circuit, a phase status register and a multiplexer. The sampler oversamples k*B bit... | 03/17/2009 |
| 7489743 | Recovery circuits and methods for the same A recovery circuit may include a phase detector, a quadrant decision unit, a quadrant controller, a charge pump unit, and a phase interpolator. The phase detector may compare a phase of input data with a phase of a current output clock to generate first up signal an... | 02/10/2009 |
| 7443929 | Method and circuit for adaptive control of the bandwidth of a carrier recovery loop in radio transmission systems A method for adaptively controlling bandwidth of a carrier recovery loop in radio transmission systems, wherein the phase error in a PLL is adjusted to a minimum level by means of a loop filter incorporated in said PLL. The phase noise value in the local oscillator ... | 10/28/2008 |
| 7443930 | Complex digital phase locked loop for use in a demodulator and method of optimal coefficient selection A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a... | 10/28/2008 |
| 7443879 | Communication between user agents through employment of codec format unsupported by one of the user agents An apparatus in one example comprises one or more network controllers that serve to allow a second user agent to communicate with a first user agent through employment of a codec format unsupported by the first user agent. ... | 10/28/2008 |
| 7440518 | Phase-locked loop circuit A PLL circuit comprises a controller (DRC) adjusting the frequency of frequency modulated signals (uDIV) provided by a frequency modulator (DIV) on the basis of signals provided by a linear range detector (LRD) so that the phase detector gets back into a ... | 10/21/2008 |
| 7439813 | Method and system for generating carrier frequencies for UWB application Apparatus and method for generating first, second and third carrier frequencies of 3432 MHz, 3960 MHz and 4488 MHz respectively, for use in a wireless transmission system deploy only first and second PLLs which are configured to generate 6336 MHz and 2640 MHz signal... | 10/21/2008 |
| 7426247 | Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes:(1) a central frequency synthesizer configured to provide both i... | 09/16/2008 |
| 7423987 | Feeder link configurations to support layered modulation for digital signals Systems and methods are disclosed for feeder link configurations to layered modulation. One feeder link system employs feeder link spot beam to antennas in distinct coverage areas to enable frequency reuse. Another system employs narrow beam width feeder link antenn... | 09/09/2008 |
| 7424068 | Method and system for coding/decoding signals and computer program product therefor A method for decoding signals with encoded symbols over a symbol interval that modulate a carrier. The method includes phase locking the signal to be decoded to obtain a phase-locked signal. The value assumed by the phase-locked signal on at least one subinterval in... | 09/09/2008 |
| 7424278 | Low IF mixer with improved selectivity performance A low IF mixer and method for down-converting a signal at a desired frequency are disclosed with improved selectivity performance. The energy of sidebands on each side of the desired frequency is evaluated; and a local oscillator frequency is selected based on the e... | 09/09/2008 |
| 7421043 | Method and/or apparatus for stabilizing the frequency of digitally synthesized waveforms An apparatus comprising a first circuit, a second circuit, a third circuit and a fourth circuit. The first circuit may be configured to generate a demodulated signal in response to (i) a modulated signal and (ii) a seed value. The second circuit may be configured to... | 09/02/2008 |
| 7421052 | Oscillator frequency selection According to some embodiments, a frequency adjuster adjusts a frequency of an oscillator. For example, the frequency adjuster might include a plurality of capacitors that are selectable using a digital control signal, and selection logic may adjust the digital contr... | 09/02/2008 |
| 7418040 | Method and apparatus for determining a timing offset for processing a multi-carrier signal A receiver 200 as a component in a wireless communication device 100 and a corresponding method are used for receiving a multi-carrier communication signal and determining a timing offset thereof. The receiver 200 comprises a controller 222 | 08/26/2008 |
| 7415081 | Orthogonal frequency division multiple signal reception apparatus, reception apparatus, orthogonal frequency division multiple signal reception method, and reception method Reception timing of a signal consisting of a valid symbol section and a guard interval section is controlled properly. According to a result of auto-correlation calculation performed by a guard correlation processor, a timing adjustment block generates a control vol... | 08/19/2008 |
| 7412010 | Frequency correction in a mobile radio receiver using an analogue and a digital control loop A mobile communication system is provided with a system for frequency correction in a reception apparatus which has a first control system, device or loop for detecting a frequency discrepancy in received signals and for appropriate correction of the frequency suppl... | 08/12/2008 |
| 7412215 | System and method for transitioning from one PLL feedback source to another A system and method are provided for switching from one phase-locked loop feedback source to another in a radio frequency (RF) transmitter. The RF transmitter includes a phase-locked loop (PLL) that provides a phase-modulated RF input signal and power amplifier circ... | 08/12/2008 |
| 7409028 | Clock synchronization in a communications environment A method and system provide a stable reference clock for use in a communication system. A phase-locked loop (PLL) receives an input clock signal with potentially unacceptable levels of jitter and wander. The PLL provides a synchronized output clock with significantl... | 08/05/2008 |
| 7406139 | System and method to identify a modulation format of a data frame within a cellular wireless network The modulation format of a data block (frame) received from a servicing base station by a wireless terminal in a cellular wireless communication system is identified. This involves first receiving several radio frequency (RF) bursts of one data block (frame) from th... | 07/29/2008 |
