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...Daniel Webster invented a "bull plow" to pull out tree stumps. It didn't catch on because it was huge and required four oxen to pull it!
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| Number | Title | Issue Date |
| 7583749 | Digital data transmitting apparatus A transmitting circuit 10 converts transmission data to a multilevel analog signal suitable for transmission. The multilevel analog signal is output to a cable 21 via an amplifier and a hybrid circuit 12. In the transmitting circuit 10, a... | 09/01/2009 |
| 7466760 | Systems and methods of RF power transmission, modulation, and amplification, including transfer function embodiments Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one... | 12/16/2008 |
| 7421036 | Systems and methods of RF power transmission, modulation, and amplification, including transfer function embodiments Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one... | 09/02/2008 |
| 7412215 | System and method for transitioning from one PLL feedback source to another A system and method are provided for switching from one phase-locked loop feedback source to another in a radio frequency (RF) transmitter. The RF transmitter includes a phase-locked loop (PLL) that provides a phase-modulated RF input signal and power amplifier circ... | 08/12/2008 |
| 7409028 | Clock synchronization in a communications environment A method and system provide a stable reference clock for use in a communication system. A phase-locked loop (PLL) receives an input clock signal with potentially unacceptable levels of jitter and wander. The PLL provides a synchronized output clock with significantl... | 08/05/2008 |
| 7391840 | Phase locked loop circuit, electronic device including a phase locked loop circuit and method for generating a periodic signal A phase locked loop (PLL) circuit (1) comprising a loop input (11); a phase detector section (2) for detecting a phase difference between an input signal and a reference signal. The phase detector section (2) has a detector input connected to th... | 06/24/2008 |
| 7366269 | False lock detection circuit and false lock detection method, PLL circuit and clock data recovery method, communication device and communication method, and optical disk reproducing device and optical disk reproducing method Disclosed herein is a false lock detection circuit including: a data signal input section receiving an input of a data signal; a clock signal input section receiving an input of a clock signal generated from the data signal; a pattern detector obtaining the data sig... | 04/29/2008 |
| 7356095 | Hybrid data recovery system In a data recovery circuit, multiple slicer outputs of incoming data for each data bit, e.g., one or more slicer outputs taken at or near the center of the eye and one or more slicer outputs taken at or near the leading edge and/or trailing edge of the eye, are proc... | 04/08/2008 |
| 7346099 | Network fabric physical layer A network fabric physical layer includes a driver coupled to a receiver via a bus, which implements a multiphase encoded protocol. A multiphase sequencer sequences (data or command/control) words for the driver. The driver outputs the sequenced words onto the bus as... | 03/18/2008 |
| 7342459 | Clock reproduction circuit A clock reproduction circuit receives a multi-valued input data signal to generate a reproduced clock signal with a higher accuracy. The clock reproduction circuit includes a data judgement block which judges whether or not three consecutive data are such that a fir... | 03/11/2008 |
| 7342986 | Digital PLL device A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring ... | 03/11/2008 |
| 7340024 | Parallel fractional interpolator with data-rate clock synchronization A circuit for single or parallel digital fractional interpolation of data samples has a fractional interpolator filter, an oscillator for outputting timing signals to the fractional interpolator filter, and a detector loop with a strobe feedback from the oscillator ... | 03/04/2008 |
| 7333789 | Wide-band modulation PLL, timing error correction system of wide-band modulation PLL, modulation timing error correction method and method for adjusting radio communication apparatus having wide-band modulation PLL A broadband modulation PLL includes a PLL portion containing a voltage controlled oscillator (101), a frequency divider (105), a phase comparator (104) and a loop filter (103). A frequency-dividing ratio of the frequency divider (105 | 02/19/2008 |
| 7327803 | Systems and methods for vector power amplification Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one... | 02/05/2008 |
| 7327298 | Gigabit ethernet line driver and hybrid architecture A gigabit ethernet line driver includes a transmitter having both transmitter and active hybrid outputs. The transmitter consists of a plurality of transmitter clusters each connected to both the transmitter and active hybrid outputs. Each transmitter cluster includ... | 02/05/2008 |
| 7318165 | Apparatus for managing a cache in a distributed caching environment having an event auditor and a cache auditor A distributed cache management system that minimizes invalid cache notification events is provided. A cache management system in a sending device processes outgoing cache notification events by adding information about the source server's clock. A cache management s... | 01/08/2008 |
| 7304995 | Systems and methods for packet flow control Systems and methods for transmitting packets and controlling packet flow are provided in wireless communication systems. A time stamping technique synchronizes timers/and clocks between one or more senders and receivers in a wireless communication system. Additional... | 12/04/2007 |
| 7298790 | Low frequency self-calibration of a PLL with multiphase clocks A Phase-Locked Loop with multiphase clocks is provided. The Phase-Locked Loop includes a main loop, a calibration loop, and Control Logic. The main loop includes, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Multi-Phase Vo... | 11/20/2007 |
| 7289005 | Polar modulator and a method for modulation of a signal A polar modulator contains a phase locked loop which is designed to emit a radio-frequency signal at one frequency to one output, with the frequency being derived from the reference signal and from a phase modulation signal at a control input of the phase locked loo... | 10/30/2007 |
| 7271633 | Charge pump structure for reducing capacitance in loop filter of a phase locked loop A charge pump and loop filter circuit of a phase locked loop includes a resistor, first and second capacitors, first and second input current sources for supplying first and second currents to the circuit, a first output current source for outputting the first curre... | 09/18/2007 |
| 7269215 | Equalization processing method and the apparatus for periodic fluctuation of transmission line characteristic A method used in equalization processing is provided, in which a reference signal is received and a change point of transmission line characteristics is detected. A basic frequency signal of fluctuation period of the transmission line characteristics is extracted, a... | 09/11/2007 |
| 7231008 | Fast locking clock and data recovery unit A method of synchronizing a transmitter and a receiver, comprising: receiving a transmitted serial data stream. Creating an N-bit data sample from the serial data stream. Decoding the N-bit data sample by a ring decoding technique. The ring decoding technique compri... | 06/12/2007 |
| 7230931 | Wireless access system using selectively adaptable beam forming in TDD frames and method of operation A transceiver for use in a wireless access network comprising a plurality of base stations, each of the plurality of base stations capable of bidirectional time division duplex (TDD) communication with wireless access devices disposed at a plurality of subscriber pr... | 06/12/2007 |
| 7224759 | Methods and apparatus for delay free phase shifting in correcting PLL phase offset An apparatus eliminates a differential phase shift, Δθ(f), between a double sideband suppressed carrier modulated angular rate information signal and its sinusoidal demodulation reference signal in a gyroscope angular rate sensing circuit including a signal refere... | 05/29/2007 |
| 7224737 | Method and apparatus employing PAM-5 coding with clock embedded in data stream and having a transition when data bits remain unchanged To significantly reduce mobile station static power consumption, and to make it possible to use a high speed asynchronous link in the mobile station, the invention uses one of the amplitude levels of, preferably, a PAM-5 (Pulse Amplitude Modulation with five amplitu... | 05/29/2007 |
| 7221715 | Timing recovery device Timing recovery device for recovering a symbol clock from a received broadcasting signal, wherein a sign is used as a timing error, which is extracted from a result of multiplication of a difference of two symbol samples and an intermediate sample thereof, thereby v... | 05/22/2007 |
| 7212580 | Multi-level signal clock recovery technique Clock recovery of a multi-level (ML) signal can be performed in a two-step process. First, the transitions within the ML signal can be detected by a novel transition detector (TD). And second, the output of the TD circuit can comprise a pseudo-non-return-to-zero (pN... | 05/01/2007 |
| 7176823 | Gigabit ethernet line driver and hybrid architecture A gigabit ethernet line driver includes a transmitter having both transmitter and active hybrid outputs. The transmitter consists of a plurality of transmitter clusters each connected to both the transmitter and active hybrid outputs. Each transmitter cluster includ... | 02/13/2007 |
| 7177385 | Shift register for safely providing a configuration bit The invention relates to a shift register cell for safely providing a configuration bit having a master latch which can be connected to a serial data input on the shift register cell for the purpose of buffer storing a data bit; a first slave latch which can be conn... | 02/13/2007 |
| 7164635 | Method of estimation parameter adaptability adjustment of an optical storage device A method of estimation parameter adaptability adjustment of an optical storage device. The method determines an estimation parameter according to a current data recording location of the optical storage device to estimate a channel bit rate. The method includes prov... | 01/16/2007 |
| 7161436 | Charge pump structure for reducing capacitance in loop filter of a phase locked loop A charge pump and loop filter circuit of a phase locked loop includes a resistor, a capacitor, first and second input current sources for supplying first and second currents to the circuit, a first output current source for outputting the first current from the circ... | 01/09/2007 |
| 7146135 | Method and adjusting transmission times in a mobile radio system In a method of adjusting transmit times at the radio interface between network and mobile stations in a mobile radio system adjustments effected by the mobile stations are controlled by the network. ... | 12/05/2006 |
| 7106759 | Network timing reference for an integrated services hub A method and apparatus for synchronizing the sampling rate of digital cells in an integrated services hub. A timing signal is extracted from an asymmetric digital subscriber line. A phase-locked loop modifies the frequency of the extracted signal and generates an ad... | 09/12/2006 |
| 7099400 | Multi-level pulse amplitude modulation receiver Multiple-level phase amplitude (M-PAM) clock and data recovery circuitry uses information from multiple phase detectors to generate one or more data sampling clocks that are optimized for each of the data slicers. One possible 4-PAM implementation includes 3 data sl... | 08/29/2006 |
| 7099423 | Method and circuit arrangement for detecting synchronization patterns in a receiver Radio frequency receivers are implemented in a variety of embodiments. In one such embodiment, a radio frequency receiver is implemented for detecting synchronization patterns in a receiver, particularly in a UHF receiver or a VHF receiver, by which the average curr... | 08/29/2006 |
| 7099424 | Clock data recovery with selectable phase control A clock data recovery (CDR) circuit to recover a clock signal and data signal from an input signal. The CDR circuit includes a control circuit, a select circuit and a phase adjust circuit. The control circuit generates a first control signal according to a phase rel... | 08/29/2006 |
| 7095819 | Direct modulation architecture for amplitude and phase modulated signals in multi-mode signal transmission Multiple-mode direct phase/amplitude modulation circuitry (20) for use in a transceiver (17) of a device such as a wireless handset (10) is disclosed. The modulation circuitry (20) includes a modulation loop (36) for modulating a p... | 08/22/2006 |
| 7046977 | Apparatus for generating multiple clock signals of different frequency characteristics A terminal includes at least one wireless communication application module (1) and a plurality of further application modules (4, 5, 6, 8). Multiple radio frequency clock signals are generated for the different modules having respective clock frequency... | 05/16/2006 |
| 7006553 | Analog signal separator for UWB versus narrowband signals A system, method, and computer program product for removing “narrowband” interference from a broader spectrum containing a UWB signal, in a receiver of the UWB signal. The RFI is extracted from a broader spectrum to remove interference from the UWB signal, by em... | 02/28/2006 |
| 6993095 | Phase-locked loop initialization via curve-fitting A method and apparatus for accurately estimating the carrier frequency offset and the carrier phase offset of a digitally modulated signal using a signal processing algorithm to initialize the state variables of a Phase-Locked Loop (PLL) is disclosed. A sequence of ... | 01/31/2006 |
