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| Number | Title | Issue Date |
| 8446978 | Communication system According to an aspect of an embodiment, a communication system includes a transmission apparatus with a coding section that generates multi-level-coded signals and transmits the multi-level-coded signals; and a deskew signal generation section that generates and tr... | 05/21/2013 |
| 8270526 | Communication system According to an aspect of an embodiment, a communication system includes a transmission apparatus with a coding section that generates multi-level-coded signals and transmits the multi-level-coded signals; and a deskew signal generation section that generates and tr... | 09/18/2012 |
| 8213532 | Information processing device and bidirectional transmission method In a provided information processing device, a first information processing module, within its transmission time segment, transmits an encoded signal in which mutually distinct first and second bit values are respectively expressed by pluralities of mutually distinc... | 07/03/2012 |
| 8054907 | Waveform analyzer A method and system for removing the effect of intersymbol interference (ISI) from a data record indicating times of logic level transitions exhibited by a data signal that has been distorted by ISI exhibited by a system having a particular step response may perform... | 11/08/2011 |
| 8027560 | System and method for synchronizing playback of audio and video A system and method for providing a digital In-Flight Entertainment (IFE) system in a vehicle, such as an aircraft, that is capable of presenting a video program and associated audio in a synchronized manner to a large number of individual video monitors and speaker... | 09/27/2011 |
| 7787558 | Rapid re-synchronization of communication channels A method of synchronizing a receiver with a transmitter. The method includes determining number of bits, j, for adjusting a bit stream, where the bit stream is generated from n tones and is dividable into codewords having a codeword length of N bytes, and the number... | 08/31/2010 |
| 7430232 | Method and system for broadcasting a programme Method and apparatuses for broadcasting and receiving a programme are presented. A programme is broadcast from a broadcasting system. Broadcast programme-associated data is transferred from a server to a cellular radio network. The broadcast programme-associated dat... | 09/30/2008 |
| 7366267 | Clock data recovery with double edge clocking based phase detector and serializer/deserializer A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholl... | 04/29/2008 |
| 7366244 | Method and system for antenna interference cancellation A wireless communication system can comprise two or more antennas that interfere with one another via free space coupling, surface wave crosstalk, dielectric leakage, or other interference effect. The interference effect can produce an interference signal on one of ... | 04/29/2008 |
| 7363371 | Traffic flow management in a communications network Admission of rapidly varying traffic flows to a communications network is controlled by sampling the traffic flows each at an ingress, and sampling an aggregate flow of said flows at some or all of the resources used by the aggregate flow. From this sampling, a mean... | 04/22/2008 |
| 7340024 | Parallel fractional interpolator with data-rate clock synchronization A circuit for single or parallel digital fractional interpolation of data samples has a fractional interpolator filter, an oscillator for outputting timing signals to the fractional interpolator filter, and a detector loop with a strobe feedback from the oscillator ... | 03/04/2008 |
| 7334152 | Clock switching circuit A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first clock and the second clock, and to make a level of the clock fixed to... | 02/19/2008 |
| 7327114 | Fan control utilizing bi-directional communications A system and method for bi-directional communication between a system controller and a fan controller: The system operates in two modes and there are two communication paths between the system controller and the fan controller. The first communication path provides ... | 02/05/2008 |
| 7308048 | System and method for selecting optimal data transition types for clock and data recovery A clock recovery circuit samples an incoming data stream that includes sequences of signal transitions. A transition detector categorizes the received signal transitions into various types, such as those associated with 2PAM and 4PAM signaling schemes. Select logic ... | 12/11/2007 |
| 7301484 | Data decoder A method, apparatus and computer program for decoding a data stream. The method comprises the steps of acquiring an analog data signal, determining an initial polarity of the analog data signal, determining a threshold transition level, determining a plurality of tr... | 11/27/2007 |
| 7280629 | Method and apparatus for receiving data based on tracking zero crossings Conventional receiver architectures are based on either frequency/phase tracking or oversampling. Both receiver types typically employ sensitive analog circuits, which create noise, consume power and utilize valuable space in their implementation. The invention adop... | 10/09/2007 |
| 7278071 | Receiving circuit for receiving message signals The invention relates to a receiving circuit for receiving message signals, having a sampler for converting the message signal into a sampled signal, an analyzing unit for decoding the sampled signal and checking it for errors, and a control unit for controlling the... | 10/02/2007 |
| 7272194 | Method to transmit bits of data over a bus A method to increase data transmission over a SCSI bus is provided including assigning a voltage level to each one of a plurality of bit combinations, and generating a signal level having the voltage level corresponding to one of the plurality of bit combinations so... | 09/18/2007 |
| RE39832 | Optical recording disk capable of resynchronization in digital encoding and decoding In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES a... | 09/11/2007 |
| 7269212 | Low-latency equalization in multi-level, multi-line communication systems Low-latency equalization mechanisms for multi-PAM communication systems are disclosed that reduce delay and complexity in signal correction mechanisms. The equalization mechanisms tap into input signals for a multi-PAM signal driver, and compensate for attenuation a... | 09/11/2007 |
| 7251256 | Synchronization of asynchronous networks using media access control (MAC) layer synchronization symbols A method and structure for the distribution and utilization of synchronization within an asynchronous network is described herein. Synchronization is distributed through an asynchronous network via a synchronization symbol periodically inserted on the MAC layer. The... | 07/31/2007 |
| 7239813 | Bit synchronization circuit and central terminal for PON systems A bit synchronization circuit composed of a multiphase data sampling unit for converting each received burst data sets to multiphase data trains, a phase determination unit for generating a control signal indicating an optimum phase data train, an output data select... | 07/03/2007 |
| 7231008 | Fast locking clock and data recovery unit A method of synchronizing a transmitter and a receiver, comprising: receiving a transmitted serial data stream. Creating an N-bit data sample from the serial data stream. Decoding the N-bit data sample by a ring decoding technique. The ring decoding technique compri... | 06/12/2007 |
| 7212580 | Multi-level signal clock recovery technique Clock recovery of a multi-level (ML) signal can be performed in a two-step process. First, the transitions within the ML signal can be detected by a novel transition detector (TD). And second, the output of the TD circuit can comprise a pseudo-non-return-to-zero (pN... | 05/01/2007 |
| 7180958 | Technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system A technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting f... | 02/20/2007 |
| 7180959 | Technique for utilizing spare bandwidth resulting from the use of a code in a multi-level signaling system A technique for utilizing spare bandwidth resulting from the use of a code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting from the use of a cod... | 02/20/2007 |
| 7180957 | Technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system A technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting f... | 02/20/2007 |
| 7173994 | Timing recovery circuit with multiple stages A timing recovery circuit includes a first oscillating circuit configured to produce a first timing signal, a second oscillating circuit configured to produce a second timing signal, a first decimation circuit coupled to a supply node of a first clock signal and to ... | 02/06/2007 |
| 7141950 | Fan control utilizing bi-directional communication A system and method for bi-directional communication between a system controller and a fan controller: The system operates in two modes and there are two communication paths between the system controller and the fan controller. The first communication path provides ... | 11/28/2006 |
| 7142605 | Method to transfer data without a clock or strobe signal A method of communicating a data bit between memory devices is disclosed, having the steps of: indicating a first value of the data bit by transitioning, between state values, a first signal applied to a first communication line interconnecting the devices; and indi... | 11/28/2006 |
| 7126408 | Method and apparatus for receiving high-speed signals with low latency An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time inter... | 10/24/2006 |
| 7123578 | Communication system for driving pairs of twisted pair links A communications system includes tow high speed communication links formed by pairs of transformers at either end thereof. A phantom circuit formed by the pairs of transformers is used to distribute power to devices connected to the high speed links. In transmission... | 10/17/2006 |
| 7123676 | Method and system for antenna interference cancellation A wireless communication system can comprise two or more antennas that interfere with one another via free space coupling, surface wave crosstalk, dielectric leakage, or other interference effect. The interference effect can produce an interference signal on one of ... | 10/17/2006 |
| 7123678 | RZ recovery A data and clock recovery system adapted for use with RZ data. In one embodiment a phase detector provides phase information for low to high data signal transitions only. In another embodiment a clock recovered from rising transitions is mixed with a clock recovered... | 10/17/2006 |
| 7102662 | Data sequence conversion circuit and printer using the same Disclosed is a data sequence conversion circuit for converting a plurality of input data sequences having different data widths into output data sequences having a prescribed data width without converting the input data sequences into serial data. The data sequence ... | 09/05/2006 |
| 7099400 | Multi-level pulse amplitude modulation receiver Multiple-level phase amplitude (M-PAM) clock and data recovery circuitry uses information from multiple phase detectors to generate one or more data sampling clocks that are optimized for each of the data slicers. One possible 4-PAM implementation includes 3 data sl... | 08/29/2006 |
| 7085339 | Data recovery device A data recovery device for precisely recovering a transmission signal even if the signal having phase variations is provided. The device comprises a demodulator for demodulating a transmission signal, a plurality of symbol recovery units, each generating a correspon... | 08/01/2006 |
| 7072406 | Serial interface and method for transferring digital data over a serial interface A digital serial interface connects a transmitting device with a receiving device for communicating both data bits and synchronization signals via the serial interface. The transmitting device include a primary transmitter for converting a serial sequence of the dat... | 07/04/2006 |
| 7068731 | Apparatus and method for multi-channel receiver A receiver for use in a communications system that employs digitally modulated signals operating in a band of frequencies that is divided into two or more non-overlapping channels, with each channel occupying no more than a predetermined maximum frequency band opera... | 06/27/2006 |
| 7065101 | Modification of bus protocol packet for serial data synchronization An apparatus for enabling transmission of parallel data from a first parallel bus to a second parallel bus via a serial data channel includes a first logic element that generates a synchronization character used in a serial data transmission protocol upon detection ... | 06/20/2006 |
