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| Number | Title | Issue Date |
| 8155235 | Modulation device and demodulation device Provided is a modulation device which generates a phase modulation signal and an amplitude modulation signal and can correct an I/Q orthogonal shift and reduce degradation of the ON/OFF ratio. In the device, a phase shifter (174) controls voltage applied to a... | 04/10/2012 |
| 8144801 | Satellite communication system utilizing low density parity check codes An approach for reliably communicating over a satellite in support of a communication service including, for example, as direct broadcast satellite and data service, is disclosed. An input message is encoded, yielding a structured Low Density Parity Check (LDPC) cod... | 03/27/2012 |
| 7978782 | Method and system for polar modulation using a direct digital frequency synthesizer Methods and systems for polar modulation using a digital direct frequency synthesizer (DDFS) are disclosed and may comprise generating a phase modulated signal in a DDFS, amplitude modulating the generated phase modulated signal in a non-linear device and transmitti... | 07/12/2011 |
| 7916804 | Method and system for a fast-switching phase-locked loop using a direct digital frequency synthesizer Aspects of a method and system for a fast-switching Phase-Locked Loop using a Direct Digital Frequency synthesizer may include generating a second signal from a first signal by: translating an inphase component of said first signal in frequency via a filtered fast-s... | 03/29/2011 |
| 7826550 | Method and system for a high-precision frequency generator using a direct digital frequency synthesizer for transmitters and receivers Aspects of a method and system for a high-precision frequency generator using a direct digital frequency synthesizer for transmitters and receivers may include generating a second signal from a first signal by frequency translating an inphase component of the first ... | 11/02/2010 |
| 7646824 | Method and system for a fast-switching phase-locked loop using a direct digital frequency synthesizer Aspects of a method and system for a fast-switching Phase-Locked Loop using a Direct Digital Frequency synthesizer may include generating a second signal from a first signal by: frequency translating an inphase component of the first signal utilizing a filtered fast... | 01/12/2010 |
| 7529313 | Distortion compensation quadrature modulator and radio transmitter An apparatus includes: an affine transformer that subjects input complex IF signals I(t) and Q(t) to affine transformation according to affine transformation coefficients, and outputs compensated signals a(t) and b(t); a quadrature modulator that applies quadrature ... | 05/05/2009 |
| 7440515 | System and method for controlling modulation A system and method for controlling modulation. The system includes a plurality of modulators and a transmitting unit. The plurality of modulators decodes data from a data signal and also encodes the data into a clock signal. The transmitting unit transmits the enco... | 10/21/2008 |
| 7363570 | Method of converting parity check matrix for low density parity check coding A method of converting a parity check matrix for low density parity check coding comprising moving rows and columns of the parity check matrix such that the parity check matrix includes a lower triangular submatrix. A calculation load for creating parity information... | 04/22/2008 |
| 7359457 | Transmission apparatus, reception apparatus and digital radio communication method A transmission apparatus includes a frame configuration determiner that determines a modulation system from among a plurality of modulation systems on a communication situation. A first symbol generator modulates a digital transmission signal according to the modula... | 04/15/2008 |
| 7352775 | Partial duplex frequency domain modulator system and method In a multi-carrier transmission scheme (frequency domain multiplexed—FDM), a single high rate data stream is split into multiple lower rate data streams each transmitted over a different carrier (e.g., a tone or bin). The data rate possible from a multiple-carrier... | 04/01/2008 |
| RE40206 | Communication system At the transmitter side, carrier waves are modulated according to an input signal for producing relevant signal points in a signal space diagram. The input signal is divided into, two, first and second, data streams. The signal points are divided into signal point g... | 04/01/2008 |
| RE40134 | Communication system At the transmitter side, carrier waves are modulated according to an input signal for producing relevant signal points in a signal space diagram. The input signal is divided into, two, first and second, data streams. The signal points are divided into signal point g... | 03/04/2008 |
| 7336748 | DDS circuit with arbitrary frequency control clock A test system using direct digital synthesis for generation of a spectrally pure, agile clock. The clock is used in analog and digital instruments in automatic test system. A DDS circuit is synchronized to the tester system clock because it is clocked by a DDS clock... | 02/26/2008 |
| 7336940 | Frequency conversion techniques using antiphase mixing A frequency upconverter using mixers operating on one or more signals and inverted versions thereof and a subtractor, such as a balun, for subtractively combining the mixer outputs to produce an upconverted signal. ... | 02/26/2008 |
| 7334181 | Method and system for providing short block length low density parity check (LDPC) codes An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a short LDPC code by shortening longer mother codes. The short LDPC code has an outer Bose Chaudhuri Hocquenghem (BCH) code. According to another aspect, for an L... | 02/19/2008 |
| 7330505 | Equaliser apparatus and methods An equalizer for a digital communications system includes a first buffer to store received data prior to equalisation; a second buffer to store error-checked received data; a channel estimator coupled to the first and second buffers to determine a channel estimate u... | 02/12/2008 |
| 7305046 | I/Q modulator with carrier predistortion An I/Q modulator used for processing an I/Q signal to obtain a predistorted output signal. The I/Q signal has an I component and a Q component, and comprises a predistorter for predistorting, with a predistortion signal, a carrier signal, which comprises a first sub... | 12/04/2007 |
| 7302235 | Synchroniser A synchroniser for use in a receiver which receives signals, wherein the synchronizer provides a digital control signal, the control signal defining a plurality of different levels; controls the level provided by successive ones of the control signals, successive on... | 11/27/2007 |
| 7286597 | Methods and systems for adaptive receiver equalization Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive contr... | 10/23/2007 |
| 7286809 | Method and circuit system for suppressing noise in a signal processing circuit Noise impulses are suppressed in a signal processing circuit by gating an input signal. The gated signal is then smoothed upstream of demodulating the smoothed signal as viewed in a signal flow direction from a signal input to a processed signal output. The signal p... | 10/23/2007 |
| 7272522 | Method and systems for optimizing high-speed signal transmission A method and systems for automatically adjusting the parameters of signal emitter in a synchronous high-speed transmission system, is disclosed. According to the method of the invention, the quality of a high-speed received signal is analyzed for a plurality of sets... | 09/18/2007 |
| 7263148 | Source synchronous CDMA bus interface A wireless IC interconnect system and a source synchronous CDMA (SS-CDMA) bus interface facilitate interconnections between first and second IC locations. A signal conveyed using the wireless system is modulated and capacitively coupled to a transmission medium, and... | 08/28/2007 |
| 7263651 | Method and apparatus for varying lengths of low density party check codewords A method and apparatus for encoding/decoding information using low density parity check (LDPC) codewords of varying lengths. In one implementation, an encoder/decoder uses a parity check matrix having a size that corresponds to a length of information for each codew... | 08/28/2007 |
| 7260361 | Locating interfering devices in wireless networks using channel adaptation metrics A method, apparatus and system relate to detecting an interfering device in a wireless network such as a wireless local area network (WLAN). In wireless networks using orthogonal frequency division multiplexing (OFDM) and adaptive bit loading (ABL), adaptive modulat... | 08/21/2007 |
| 7239846 | Up-conversion modulation loop for multi-mode mobile communication The present invention relates to a signal modulation loop for the multi-mode mobile communication. The adaptive up-conversion modulation loop is applied in the multi-mode mobile communication, and is used for signal integration for the communication system comprisin... | 07/03/2007 |
| 7230993 | Method and apparatus for modulation using an at least four-dimensional signal constellation A digital communication system (20) in which a signal constellation (30) of a dimensionality of at least four is used, with distance properties chosen to reduce the bit error rate compared to that of digital communication systems using signal constella... | 06/12/2007 |
| 7228100 | Program data display in duplicative digital audio broadcasting system Program data is provided in association with a main audio program to a receiver of a duplicative radio broadcasting system wherein a duplicative broadcast (such as a hybrid IBOC broadcast) includes a primary channel and a backup channel in a predetermined frequency ... | 06/05/2007 |
| 7221718 | I/Q demodulator and I/Q signal sampling method thereof An I/Q demodulator optimized with a minimum amount of hardware. First and second multiplexers generate I and Q signals with respect to an input data signal; and first and second 2-decimation units decimate the I and Q signals generated by the first and second multip... | 05/22/2007 |
| 7214189 | Methods and apparatus for tissue activation and monitoring Techniques for controlling one or more modular circuits (“satellites”) that are intended for placement in a subject's body. The one or more satellites are controlled by sending signals over a bus that includes first and second conduction paths. Also coupled to t... | 05/08/2007 |
| 7203887 | Method and system for routing in low density parity check (LDPC) decoders An approach is provided for decoding a low density parity check (LDPC) coded signal. Edge values associated with a structured parity check matrix used to generate the LDPC coded signal are retrieved from memory. The edge values specify the relationship of bit nodes ... | 04/10/2007 |
| 7199615 | High speed signaling system with adaptive transmit pre-emphasis and reflection cancellation A signaling system having an equalizing transmitter and equalizing receiver. The equalizing transmitter transmits a signal to a receive circuit. A first sampling circuit within the equalizing receiver samples the signal to determine whether the signal exceeds a firs... | 04/03/2007 |
| 7194390 | Predictor of minimal noise figure for wideband amplifier A predictor allows the computation of the greatest lower bound of the noise figure pertaining uniformly over the operating band of a wideband amplifier. This computation is done directly from noise-parameter data of the amplifier. ... | 03/20/2007 |
| 7167528 | Modulation system for modulating data onto a carrier signal with offsets to compensate for doppler effect and allow a frequency synthesizing system to make steps equal to channel bandwidth A method and system for modulating data onto a carrier signal in a plurality of channels, each of the channels having a channel bandwidth, can be created for use in any two-way satellite communication system or other wireless communication application where frequenc... | 01/23/2007 |
| 7162000 | Delay locked loop synthesizer with multiple outputs and digital modulation A delay locked loop circuit (200) in which multiple outputs are produced. A single delay line (24) is shared among multiple tap selection circuits (256A, 265B, 265C). Fixed phase shifts (412) can be introduced between multip... | 01/09/2007 |
| 7137029 | Information processor An information processor is provided with: two chip sets that are each provided with a serial controller, these chip sets being the interface between a CPU and an input/output device; a selector for switching the connection routes between the serial controllers and ... | 11/14/2006 |
| 7136626 | Radio frequency modulator A transmitter architecture (200) provides for a stable and low noise modulator where the modulation bandwidth is uncorrelated to the TX loop bandwidth. The output signal (228) of the TX loop is demodulated by a demodulator (208) and the demodula... | 11/14/2006 |
| 7136447 | Clock recovery circuit A clock recovery circuit for establishing bit synchronization with a received signal. The clock recovery circuit comprises a conventional early-late gate circuit and a loop filter. The loop filter receives an output signal of an early sample circuit included in the ... | 11/14/2006 |
| 7127002 | System and method for frequency and phase modulating data on a SCSI bus or a serial SCSI link A system and a method for multiplying data throughput in a SCSI bus includes identifying multiple frequencies within a bandwidth of a SCSI bus. A binary value is assigned to each one of the multiple frequencies. One of the multiple frequencies is selected. The assig... | 10/24/2006 |
| 7120202 | Wireless communication apparatus In a wireless communication apparatus which has the functions of both ASK modulation and QPSK modulation, which can be manufactured at a low cost, and which is small in size, an output terminal of a QPSK modulator is connected to a carrier wave input terminal of an ... | 10/10/2006 |