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| Number | Title | Issue Date |
| 7443909 | Weighted autocorrelation method for downlink CDMA LMMSE equalizers Receiving downlink CDMA signals in a fast-fading environment is facilitated at higher receiver velocities by updating the block-adaptive linear minimum mean square error (LMMSE) downlink CDMA equalizer. The autocorrelation matrix of the observed data is updated by p... | 10/28/2008 |
| 7443913 | High speed decision feedback equalizer An equalizer comprises a sampler, a filter, and a summer. The sampler samples a signal indicative of an input communication signal to determine digital decision output signals having a communication device data rate. The filter receives digital decision output signa... | 10/28/2008 |
| 7440512 | Electrical signal regenerator An electrical signal regenerator including an equalizer and a clock data recovery circuit is provided. The clock data recovery circuit is selected when an input signal of a higher bitrate multiplex level is detected, but the clock data recovery circuit is bypassed w... | 10/21/2008 |
| 7440499 | Fractional spaced equalizer Fractional Spaced Equalizer FSEQ having adjustable coefficients ci for equalizing a reception signal of a transceiver. The transceiver comprises an echo compensator EC which generates an echo compensation signal for compensating an echo signal of the transceiver. Th... | 10/21/2008 |
| 7433418 | Method and apparatus for efficient storage of training sequences for peak to average power constrained modulation formats Some embodiments store a training sequence in a communications system. The stored training sequence exhibits certain desirable characteristics when used by a peak to average power constrained modulation format. In one embodiment, a set of original ordered sequences ... | 10/07/2008 |
| 7421021 | Adaptive signal equalizer with adaptive error timing and precursor/postcursor configuration control An adaptive signal equalizer with a feedforward filter in which the feedback error signal and corresponding incoming data signal are dynamically aligned in time using signal interpolation, and further, to control the precursor/postcursor filter taps configuration, t... | 09/02/2008 |
| 7406122 | Equalizer and method of setting initial value for same An equalizer is provided which is capable of making a filter factor to be set in the equalizer having an equalizing filter converge rapidly and a method is provided for setting an initial value for the rapid convergence of the filter factor. In the equalizer having ... | 07/29/2008 |
| 7394849 | Decision feedback equalizer with dynamic feedback control A decision feedback equalizer with dynamic feedback control for use in an adaptive signal equalizer. Timing within the decision feedback loop is dynamically controlled to optimize recovery of the data signal by the output signal slicer. The dynamic timing is control... | 07/01/2008 |
| 7386044 | Computation of decision feedback equalizer coefficients with constrained feedback tap energy A Decision Feedback Equalizer (DFE) system includes a DFE and a DFE coefficients processor. The DFE receives an uncompensated signal and operates upon the uncompensated input using DFE coefficients to produce an equalized output. The DFE coefficients processor formu... | 06/10/2008 |
| 7382827 | Computation of decision feedback equalizer coefficients with constrained feedback tap energy Directly computing Feed Forward Equalizer (FFE) coefficients and Feed Back Equalizer (FBE) coefficients of a Decision Feedback Equalizer (DFE) from a channel estimate. The FBE coefficients have an energy constraint. A recursive least squares problem is formulated ba... | 06/03/2008 |
| 7369607 | Multicarrier communication using a time domain equalizing filter Various methods and apparatus are described that use a filter. A receiver may be configured to receive multi-tone signals. The receiver has a Time Domain Equalizer filter employing an algorithm to shorten a length of an incoming impulse response to equal to or less ... | 05/06/2008 |
| 7362799 | Method and apparatus for communication signal resolution Embodiments of the present invention provide methods and apparatuses for determining a parameter value for each of a plurality of communication signals received concurrently as a composite signal. The parameter value of each communication signal is within a correspo... | 04/22/2008 |
| 7362800 | Auto-configured equalizer An signal communication device having an auto-configured equalizer. The signal communication device includes a scoping circuit, buffer circuit, select circuit and equalizing circuit. A test signal is transmitted to the signal communication device via a signal path. ... | 04/22/2008 |
| 7352815 | Data transceiver and method for equalizing the data eye of a differential input data signal Apparatus and method for counteracting high frequency attenuation of a differential input data signal as the signal is conducted through a data link. A differential input data signal is transmitted from a transmitter to a receiver through a data link. The data eye o... | 04/01/2008 |
| 7349489 | Pulse shaping filter with minimal intersymbol interference An improved shaping filter (R) is provided in a radio frequency communication system. The filter response of the shaping filter (R) is generated by constraining the filter coefficients in their adaptation at the optimal sampling point and not constraining them at th... | 03/25/2008 |
| 7346105 | Decision feedback equalization with fractionally-spaced feedback data A decision feedback equalizer (DFE) architecture uses feedback samples that are over-sampled with respect to the symbol rate. On-baud feedback samples are quantized with a slicer, while off-baud samples are linear, IIR samples. Both forward and feedback filters are ... | 03/18/2008 |
| 7339988 | Channel monitoring and identification and performance monitoring in a flexible high speed signal processor engine Systems and methods are disclosed to provide channel monitoring and/or performance monitoring for a communication channel. For example, in accordance with an embodiment of the present invention, an equalizer is disclosed that equalizes for channel distortions and al... | 03/04/2008 |
| 7336729 | Digital signal processing based de-serializer A DSP based SERDES performs compensation operations to support high speed de-serialization. A receiver section of the DSP based SERDES includes one or more ADCs and DSPs. The ADC operates to sample (modulated) analog serial data and to produce digitized serial data ... | 02/26/2008 |
| 7333539 | High order filters with controllable delay and performance A digital filter is disclosed, the filter comprising a device for determining the initial condition of a partial filter input, using a partitioned filter input signal, and partitioned filter input coefficients and a device for determining the initial condition of a ... | 02/19/2008 |
| 7333576 | Digital demodulation device and synchronization detecting method A synchronization error occurs when a DTV signal is distorted on a transmission path and this deteriorates demodulation capability. The digital demodulation device and the synchronization detecting method of the invention can correct the synchronization position whe... | 02/19/2008 |
| 7327808 | Pipelined adaptive decision feedback equalizer A pipelined adaptive decision feedback equalizer (DFE). The pipelined ADFE comprises a pre-processing unit, an adder, a feedback filter (FBF), a slicer, a delay unit, a weight-update block and a mapping circuit. The pre-processing unit comprising a plurality of PP c... | 02/05/2008 |
| 7324589 | Method and system for providing error compensation to a signal using feedback control A method for providing error compensation to a signal includes providing error adjustment to a signal at a transmitter and communicating the signal over a channel at a channel speed. The method includes receiving the signal from the channel at the channel speed and ... | 01/29/2008 |
| 7319719 | Parallel equalization for systems using time division multiple access An equalization circuit is provided. The equalization circuit includes an input adapted to receive signals from a communications channel. The equalization circuit further includes a plurality of equalizer circuits coupled to the input and operable to generate a plur... | 01/15/2008 |
| 7317772 | Multi-mode variable rate digital cable receiver Carrier signals modulated by information (video and/or data) signals are received through a cable and are converted to modulated signals at an intermediate frequency. The IF signals are sampled at a particular frequency to produce digital information signals. The di... | 01/08/2008 |
| 7313181 | Calibration of scale factor in adaptive equalizers An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: h(t+1)= h(t)+μ[sgn{... | 12/25/2007 |
| 7313199 | Power amplifier linearization A system for linearizing the output of a high power amplifier (HPA) designed to transmit an RF modulated signal includes in its transmit section a digital up-converter for processing baseband input signals and generating a desired digital RF waveform, T(s). The desi... | 12/25/2007 |
| 7305029 | Multi-pair gigabit ethernet transceiver Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components i... | 12/04/2007 |
| 7301997 | Method and apparatus for improved high-speed adaptive equalization A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred em... | 11/27/2007 |
| 7301998 | Filter with signal taps temporally spaced at fractional symbol intervals Described are methods and devices for processing a signal transmitting symbols which are temporally spaced on symbol intervals. The signal may be tapped at fractional symbol intervals to provide a plurality of signal taps at the fractional symbol intervals. Each of ... | 11/27/2007 |
| 7292661 | Block-iterative equalizers for digital communication system A block-iterative equalizer is adapted for use in contemporary digital communication system receivers. In a preferred embodiment, data received over a communication channel is processed by a linear feed-forward filter and the resulting filtered signal is provided to... | 11/06/2007 |
| 7292631 | Feed forward equalizer and a method for analog equalization of a data signal A feed forward equalizer for analog equalization of a data signal received over a data transmission channel comprising a Master Delay Locked Loop (MDLL) for generating equidistant reference phase signals; a Slave Delay Line (SDL) formed by serial connected Slave Del... | 11/06/2007 |
| 7289555 | Method and system for signal processing using vector output from scalar data A method for processing a signal includes receiving a signal from a channel at a channel speed and providing error adjustment to the signal. The method includes sampling the signal at a speed less than the channel speed to yield sampled scalar data. The signal is sa... | 10/30/2007 |
| 7286621 | Reception method and receiver array for a duplex transmission system The invention relates to a duplex transmission system, wherein an echo compensation signal (yec(k·t)) is generated which is combined with a receive signal (u(t)) to prevent crosstalk from the own transmitter to the receiver. Before feeding the receive signal to the... | 10/23/2007 |
| 7274762 | Calculation circuit for calculating a sampling phase error A calculation circuit for calculating a sampling phase error is provided. According to one aspect, a calculation circuit includes a first delay element chain having serially connected delay elements, for delaying a digital estimate of a decision device; a second del... | 09/25/2007 |
| 7274737 | EHF equalizer implemented with MEMs tap weight controls A signal equalizer that employs micro-electromechanical machine devices for the tap weight controllers. The equalizer includes a substrate on which is formed a forward transmission line rail and a return transmission line rail. A cantilever stanchion is also formed ... | 09/25/2007 |
| 7272174 | Upstream data transmission A process transmits digital data to an A/D converter via an analog channel. The process includes generating a sequence of output signals by precoding a sequence of input signal points to precompensate for ISI in the analog channel. In the precoding is matched to the... | 09/18/2007 |
| 7266145 | Adaptive signal equalizer with adaptive error timing and precursor/postcursor configuration control An adaptive signal equalizer with a feedforward filter in which the feedback error signal and corresponding incoming data signal are dynamically aligned in time using signal interpolation, and further, to control the precursor/postcursor filter taps configuration, t... | 09/04/2007 |
| 7266146 | Symbol-based decision feedback equalizer (DFE) optimal equalization method and apparatus with maximum likelihood sequence estimation for wireless receivers under multipath channels A maximum likelihood sequence estimator (MLSE) equalizer device being included in an MLSE sub-receiver includes a feedforward circuit responsive to input data for processing the same to generate feedforward circuit output, said input data being generated from transm... | 09/04/2007 |
| 7263123 | Fast computation of coefficients for a variable delay decision feedback equalizer Optimal Decision Feedback Equalizer (DFE) coefficients are determined from a channel estimate by casting the DFE coefficient problem as a standard recursive least squares (RLS) problem and solving the RLS problem. In one embodiment, a fast recursive method, e.g., fa... | 08/28/2007 |
| 7263134 | Ethernet transceiver with single-state decision feedback equalizer Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components i... | 08/28/2007 |
