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| Number | Title | Issue Date |
| 7835425 | Architectures, circuits, systems and methods for reducing latency in data communications Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circu... | 11/16/2010 |
| 7773665 | Apparatus and method for corresponding frequency synchronization in on-channel repeater Provided is a frequency synchronizing apparatus and method that can synchronize frequencies between receiving signals and transmitting signals by extracting a carrier error and sampling timing error information in a synchronization process of the receiving signal fr... | 08/10/2010 |
| 7486718 | Architectures, circuits, systems and methods for reducing latency in data communications Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circu... | 02/03/2009 |
| 7421053 | Fast clock acquisition enable method using phase stir injection to PLL for burst mode optical receivers Systems and methods for aligning the phase of a PLL with an incoming data signal. In one embodiment, when a data signal is received in a PLL, a phase perturbation signal is generated and injected into the PLL. The PLL then performs a phase alignment procedure to loc... | 09/02/2008 |
| 7409029 | Transmission device for automatically set an optimal point for a signal decision making There is provided a flexible transmission device capable of automatically setting an optimal point for a signal decision making with high accuracy, so that highly reliable high-quality signal regeneration control is achieved. A clock timing extraction circuit dynami... | 08/05/2008 |
| 7409028 | Clock synchronization in a communications environment A method and system provide a stable reference clock for use in a communication system. A phase-locked loop (PLL) receives an input clock signal with potentially unacceptable levels of jitter and wander. The PLL provides a synchronized output clock with significantl... | 08/05/2008 |
| 7391840 | Phase locked loop circuit, electronic device including a phase locked loop circuit and method for generating a periodic signal A phase locked loop (PLL) circuit (1) comprising a loop input (11); a phase detector section (2) for detecting a phase difference between an input signal and a reference signal. The phase detector section (2) has a detector input connected to th... | 06/24/2008 |
| 7342986 | Digital PLL device A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring ... | 03/11/2008 |
| 7339365 | Phase detector and method of phase detection In order to provide a phase detector and a method of phase detection which are distinguished by greater sensitivity and simple implementability, at least one differential signal of two input signals (Ua; Ub) may be formed over at least one pred... | 03/04/2008 |
| 7313210 | System and method for establishing a known timing relationship between two clock signals A system and method for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transpor... | 12/25/2007 |
| 7280589 | Source synchronous I/O bus retimer A device configured to recover and repeat source synchronous data. The device is configured to receive source synchronous data via a first interface and recover the received data utilizing a first clock signal which is generated to be approximately ninety degrees ou... | 10/09/2007 |
| 7263151 | High frequency loss of signal detector Methods and circuitry for implementing high speed loss-of-signal detectors for use in Gb/s telecommunication applications. The invention measures bit error rate (BER) of the incoming data by comparing the phase of the clock signal extracted from the incoming data wi... | 08/28/2007 |
| 7242740 | Digital phase-locked loop with master-slave modes A digital phase locked loop (DPLL) for providing clock synchronization in backplane bus systems has a loop filter with selectable high and low bandwidth modes. The DPLL is thus capable of respectively attenuating or tracking jitter from an input reference clock.... | 07/10/2007 |
| 7224759 | Methods and apparatus for delay free phase shifting in correcting PLL phase offset An apparatus eliminates a differential phase shift, Δθ(f), between a double sideband suppressed carrier modulated angular rate information signal and its sinusoidal demodulation reference signal in a gyroscope angular rate sensing circuit including a signal refere... | 05/29/2007 |
| 7212049 | Digital-control-type phase-composing circuit system A digital-control phase-composing circuit system has a phase-composing circuit which is supplied with two input clock signals having a phase difference therebetween and a control signal, and which composes an output clock signal having a phase between the phases of ... | 05/01/2007 |
| 7206606 | Wireless communication including diversity transmission and reception A wireless communication apparatus includes a plurality of antennas that transmit modulation signals. A controller controls a control signal of the modulation signals based on an eigenvalue corresponding to a channel matrix generated using the modulation signals rec... | 04/17/2007 |
| 7139308 | Source synchronous bus repeater A device configured to recover and repeat source synchronous data. In one embodiment, the device is configured to receive source synchronous data via a first interface, recover the received data utilizing a corresponding received source synchronous clock signal, and... | 11/21/2006 |
| 7133324 | Synchronous dynamic random access memory devices having dual data rate 1 (DDR1) and DDR2 modes of operation and methods of operating same A dual data rate dynamic random access memory (DDR DRAM) device may operate in dual DDR modes via a mode selection circuit configured to enable a Dual Data Rate (DDR) 1 mode of operation for the DDR DRAM or a DDR2 mode of operation for the DDR DRAM. | 11/07/2006 |
| 7133946 | Mechanism to repeat signals across an unrelated link According to one embodiment a system is disclosed. The system includes a first integrated circuit (IC) a first interface coupled to the first IC and a second IC coupled to the interface. The first IC transmits the state of each of a plurality of signals not associat... | 11/07/2006 |
| 7106822 | Bidirectional synchronous interface with single time base A bidirectional synchronous interface for the reception of a first flow of digital data with a first coding from a communication channel, and for the transmission on the communication channel of a second flow of digital data with the first coding in synchrony with a... | 09/12/2006 |
| 7046977 | Apparatus for generating multiple clock signals of different frequency characteristics A terminal includes at least one wireless communication application module (1) and a plurality of further application modules (4, 5, 6, 8). Multiple radio frequency clock signals are generated for the different modules having respective clock frequency... | 05/16/2006 |
| 6999480 | Method and apparatus for improving data integrity and desynchronizer recovery time after a loss of signal An apparatus and corresponding method for preventing data loss in network devices is disclosed. The present invention monitors an incoming data stream to a network device, or devices, and in the event that an error condition is detected, predetermined error data is ... | 02/14/2006 |
| 6993095 | Phase-locked loop initialization via curve-fitting A method and apparatus for accurately estimating the carrier frequency offset and the carrier phase offset of a digitally modulated signal using a signal processing algorithm to initialize the state variables of a Phase-Locked Loop (PLL) is disclosed. A sequence of ... | 01/31/2006 |
| 6959202 | Method for using applications in a mobile station, a mobile station, and a system for effecting payments The invention relates to a method for using an application (18) in a mobile station (1). The application has a first mode of operation and a second mode of operation, whereby the first mode of operation is passive, and in the second mode of operation t... | 10/25/2005 |
| 6807245 | PLO device There is provided a PLO device which performs high-accuracy, high-quality clock recovery. A shifted data generation part generates shifted data, and a first phase comparison part outputs first difference data. A first filter removes an alternating-current component ... | 10/19/2004 |
| 6754234 | Method and apparatus for asynchronous frame synchronization A method and apparatus for frame synchronization in a display circuit is achieved by first measuring a difference between a first frame period and a second frame period. When the difference exceeds a threshold, the first frame period is adjusted by replacing the clo... | 06/22/2004 |
| 6636979 | System for measuring phase error between two clocks by using a plurality of phase latches with different respective delays A phase error measurement circuit for measuring phase error between two clocks on an integrated circuit is provided. The measurement circuit includes first and second clock signal inputs, a phase lead detector, a phase lag detector and a phase error measu... | 10/21/2003 |
| 6563893 | Carrier-frequency synchronization system for improved amplitude modulation and television broadcast reception Systems and methods are described for carrier-frequency synchronization for improved AM and TV broadcast reception. A method includes synchronizing a carrier frequency of a broadcast signal with a remote reference frequency. An apparatus includes a refere... | 05/13/2003 |
| 6564160 | Random sampling with phase measurement Repetitive sampling of a data signal is performed. A clock reference is generated. The clock reference has a known period relationship with the data signal. The clock reference and the data signal are simultaneously sampled. The sampled information from t... | 05/13/2003 |
| 6516419 | Network synchronization method and non-break clock switching method in extended bus connection system A method of simple network synchronization in a bus extension system with expanded capabilities wherein a plurality of independently-operable multimedia multiplexing devices are connected to the same network in parallel. The method of network synchronizat... | 02/04/2003 |
| 6335952 | Single chip CMOS transmitter/receiver A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention includes an antenna for receiving transmitting RF signals, a PLL for generating multi... | 01/01/2002 |
| 6249560 | PLL circuit and noise reduction means for PLL circuit The frequency divider output a2 is provided to the D input of a first D flip-flop and an input clock a1 to a first frequency divider is inversed by an inverter and is then provided to the C input of the first D flip-flop. The first f... | 06/19/2001 |
| 5982812 | Method and apparatus for monitoring frequency synthesizer locking time A frequency synthesizer circuit comprises a controller, a synthesizer and a voltage controlled oscillator are used to generate an oscillating signal in response to external commands. The synthesizer provides a lock detect signal to the controller when the... | 11/09/1999 |
| 5815541 | Digital phase locked loop assembly A digital PLL apparatus includes a synchronization integrating circuit, an angle calculating circuit, and a digital PLL circuit. The synchronization integrating circuit determines a symbol timing by obtaining the maximum amplitude point of a correlation l... | 09/29/1998 |
| 5623512 | Rate converting device capable of determining a transmission rate as desired On converting an input data signal having a first transmission rate into an output data signal having a second transmission rate different from the first transmission rate, the input data signal is memorized as a memorized input data signal a first memory... | 04/22/1997 |
| 5487084 | Generation of a clock frequency in a smart card interface A circuit arrangement for generating the clock signal of a predetermined frequency f(UART) for a smart card interface, the interface being used for transferring data from a smart card to a device e.g. a mobile telephone at a predetermined data rate f(D). ... | 01/23/1996 |
| 5471502 | Bit clock regeneration circuit for PCM data, implementable on integrated circuit In a bit clock generation circuitry, a T/2 pulse generator includes a monostable multivibrator triggered by an edge of an input PCM data signal and controlled by a time constant adjusting signal so as to generate a pulse signal having its pulse width adju... | 11/28/1995 |
| 5210773 | Process for the intermediate amplification of digital signals and intermediate amplifiers for digital signals An intermediate amplification process for digital signals with pulse regeneration, determines the phase difference between the receiving timing signal and the local transmission timing signal and alters the phase of the local transmission timing signal as... | 05/11/1993 |
| 5090025 | Token ring synchronization An improved local area network node of the type described in ANSI/IEEE Standard 802.5, including a receiver-demodulator having an input connectable to the ring and having a received data output and a received clock output, an elasticity buffer connected t... | 02/18/1992 |
| 5052022 | Repeater and PLL circuit A PLL circuit for generating an AC output signal synchronized with an AC input signal applied thereto with a phase offset with respect to the input signal includes, in one embodiment, a charge pump circuit capable of varying the phase offset depending on ... | 09/24/1991 |
