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Pet Toilet-Like Water Disk and Food Storage
One pet-friendly inventor patented "a device for watering pets, e.g., a dog or cat." The device, he helpfully noted, "has the general shape of a toilet."
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| Number | Title | Issue Date |
| 8031757 | Time divided pilot channel detection processing in a WCDMA terminal having a shared memory A method for operating a Radio Frequency (RF) receiver of a wireless terminal. During a first time interval, an RF front end is enabled and the RF receiver receives and processes an RF signal, e.g., a Wideband Code Division Multiple Access (WCDMA) signal, to produce... | 10/04/2011 |
| 7436842 | Outlet with analog signal adapter, a method for use thereof and a network using said outlet An outlet for a Local Area Network (LAN), containing an integrated adapter that converts digital data to and from analog video signal. Such an outlet allows using analog video units in a digital data network, eliminating the need for a digital video units or externa... | 10/14/2008 |
| 7373114 | Signal transmission circuit, signal output circuit and termination method of signal transmission circuit This invention provides a signal transmission circuit, a signal output circuit, and a termination method of a signal transmission circuit capable of preventing the re-reflection of the signal at a transmitting node of a transmission path even when an impedance of a ... | 05/13/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7353320 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 04/01/2008 |
| 7310752 | System and method for on-board timing margin testing of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 12/18/2007 |
| 7310748 | Memory hub tester interface and method for use thereof A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command,... | 12/18/2007 |
| 7308023 | Dual function clock signal suitable for host control of synchronous and asynchronous target devices A host device in a data communication system provides a dual-function clock/enable signal at a single output port shared by at least one asynchronous target device and at least one synchronous target device. In the asynchronous operating mode, the host device genera... | 12/11/2007 |
| 7289347 | System and method for optically interconnecting memory devices A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable t... | 10/30/2007 |
| 7286567 | Telecommunications system, and methods for transmitting data, and telecommunication system synchronization method Telecommunications systems can be synchronized via the transmission link. In this process, the telecommunication systems receive the clock signal and an additional information item, which describes the quality of the clock signal, from the received data stream. In t... | 10/23/2007 |
| 7283787 | Direct amplifying station and positioning method for mobile station thereof The present invention relates to a repeater for positioning mobile station and a method thereof. The repeater according to the present invention is implemented through adding a cell identifier generator module to the downlink circuit structure of a conventional repe... | 10/16/2007 |
| 7282947 | Memory module and method having improved signal routing topology A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends ... | 10/16/2007 |
| 7278060 | System and method for on-board diagnostics of memory modules A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a ... | 10/02/2007 |
| 7272682 | Memory hub bypass circuit and method A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurali... | 09/18/2007 |
| 7272362 | Multi-sector in-building repeater A multi-sector in-building repeater, including: a master transmitting unit for receiving multi-sector signals of a carrier from a base station, mixing the multi-sector signals with different transmission intermediate frequency signals, and outputting mixed multi-sec... | 09/18/2007 |
| 7266633 | System and method for communicating the synchronization status of memory modules during initialization of the memory modules A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the memory hubs each include at least one receiver that is synchronized to an internal clock signal during in... | 09/04/2007 |
| 7260685 | Memory hub and access method having internal prefetch buffers A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history lo... | 08/21/2007 |
| 7257683 | Memory arbitration system and method having an arbitration packet protocol A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read respo... | 08/14/2007 |
| 7254331 | System and method for multiple bit optical data transmission in memory systems The disclosed system and method data increases data transmission speed through a memory system by using optical signals comprising a plurality of wavelengths of light so that each pulse of optical signals can represent more than a single bit of data. An optical tran... | 08/07/2007 |
| 7251714 | Method and system for capturing and bypassing memory transactions in a hub-based memory system A memory hub includes a reception interface that receives data words and captures the data words in response to a first clock signal in a first time domain. The interface also provides groups of the captured data words on an output in response to a second clock sign... | 07/31/2007 |
| 7249236 | Method and system for controlling memory accesses to memory modules having a memory hub architecture A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules... | 07/24/2007 |
| 7245145 | Memory module and method having improved signal routing topology A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends ... | 07/17/2007 |
| 7242213 | Memory module and method having improved signal routing topology A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends ... | 07/10/2007 |
| 7234070 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 06/19/2007 |
| 7230506 | Crosstalk reduction for a system of differential line pairs A technique is presented for minimizing crosstalk between adjacent differential signal pairs in communications. A backplane embodiment wherein the backplane includes a plurality of differential signal line pairs, is presented. A first differential signal line pair c... | 06/12/2007 |
| 7222210 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/22/2007 |
| 7222197 | Apparatus and method for direct memory access in a hub-based memory system A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a me... | 05/22/2007 |
| 7222213 | System and method for communicating the synchronization status of memory modules during initialization of the memory modules A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the memory hubs each include at least one receiver that is synchronized to an internal clock signal during in... | 05/22/2007 |
| 7213082 | Memory hub and method for providing memory sequencing hints A memory module includes a memory hub coupled to several memory devices. The memory hub is also coupled to receive a memory packet from a system controller containing a memory hint indicative of the subsequent operation of the memory devices. The memory module uses ... | 05/01/2007 |
| 7210059 | System and method for on-board diagnostics of memory modules A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a ... | 04/24/2007 |
| 7206887 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 04/17/2007 |
| 7200024 | System and method for optically interconnecting memory devices A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable t... | 04/03/2007 |
| 7194593 | Memory hub with integrated non-volatile memory A memory hub having an integrated non-volatile memory for storing configuration information is provided. The memory hub includes a high-speed interface for receiving memory access requests, a non-volatile memory having memory configuration information stored therein... | 03/20/2007 |
| 7188219 | Buffer control system and method for a memory system having outstanding read and write request buffers A memory controller and method for managing the issuance of read and write requests to a system memory is provided. The number of outstanding read requests and write requests issued to the system memory are separately monitored and further issuance of read and write... | 03/06/2007 |
| 7180522 | Apparatus and method for distributed memory control in a graphics processing system A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memor... | 02/20/2007 |
| 7181584 | Dynamic command and/or address mirroring system and method for memory modules A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored configuration with mirrored terminals of memory devices on opposite su... | 02/20/2007 |
| 7174409 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 02/06/2007 |
| 7170395 | Method and apparatus for attaching power line communications to customer premises A method and apparatus for modifying a three-phase power distribution network in a building in order to provide data communication by using a Power Line Carrier (PLC) signal to an approximate electrical central location point of Wye-connected and Delta connected pow... | 01/30/2007 |
