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"Flight by machines heavier than air is unpractical and insignificant, if not utterly impossible."
Simon Newcomb, astronomer ; Said in 1902, less than two years before the first flight at Kitty Hawk
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| Number | Title | Issue Date |
| 8072987 | Full array non-disruptive data migration Source and destination fiber channel devices are coupled to a fiber channel fabric. Hosts communicate with the fiber channel devices using fiber channel addresses. All data is copied from the source fiber channel device to the destination fiber channel device. Sourc... | 12/06/2011 |
| 8050280 | Efficient switching device and method for fabricating the same using multiple shared memories An efficient switching device and a method for fabricating the same using multiple shared memories are provided. The switching device includes: an output time determination unit to determine an output time to an output port; an output time administration unit to adm... | 11/01/2011 |
| 8040900 | N-port network adaptor Methods, systems and computer program products for an N-port network adaptor that is interchangeable between a network switch and a network adaptor. Embodiments of the invention include a method in a network device having a random access memory, a nonvolatile random... | 10/18/2011 |
| 8031722 | Techniques for controlling a network switch of a data storage system A technique controls a network switch having a set of ports. The technique involves configuring the network switch to provide an initial set of communications paths between the ports. The initial set of communications paths defines an initial communications path top... | 10/04/2011 |
| 8018951 | Pacing a data transfer operation between compute nodes on a parallel computer Methods, systems, and products are disclosed for pacing a data transfer between compute nodes on a parallel computer that include: transferring, by an origin compute node, a chunk of an application message to a target compute node; sending, by the origin compute nod... | 09/13/2011 |
| 7944931 | Balanced bandwidth utilization A memory subsystem includes Data Store 0 and Data Store 1. Each data store is partitioned into N buffers, N>1. An increment of memory is formed by a buffer pair, with each buffer of the buffer pair being in a different data store. Two buffer pair forma... | 05/17/2011 |
| 7944930 | Memory buffering with fast packet information access for a network device A networking device employing memory buffering in which a first memory is logically configured into blocks, and the blocks are logically configured into particles, where a second memory is configured to mirror the first memory in which a fixed number of bits in the ... | 05/17/2011 |
| 7936767 | Systems and methods for monitoring high speed network traffic via sequentially multiplexed data streams Systems and methods for monitoring high-speed network traffic via sequentially multiplexed data streams. Exemplary embodiments include a switch module system, including a first switch module configured to be coupled to a first server chassis, a first data port dispo... | 05/03/2011 |
| 7929549 | Method and apparatus for scrambling data for control of high-speed bidirectional signaling A memory subsystem includes a master controller that includes a pseudo random bit sequence (PRBS) generator having a plurality of output taps and an exclusive-OR (XOR) unit. The memory subsystem also includes a memory device that is coupled to the master controller ... | 04/19/2011 |
| 7869440 | Efficient splitting and mixing of streaming-data frames for processing through multiple processing modules Streaming data is processed through one or more pipes of connected modules including mixers and/or splitters. The data is carried in composite physically allocated frames having virtual subframes associated with different ones of the splitters, mixers, and other tra... | 01/11/2011 |
| 7852858 | Method and device for communication between multiple sockets One (SC3) of the sockets (SC) is designated to be capable of receiving the data stream received by each socket associated with a selected process, Said socket thereby designated (SC3) further comprises an additional receive list (RXS) listing buffer me... | 12/14/2010 |
| 7778253 | Data switch, and communication system using the data switch A preferred embodiment comprising a data switch includes a first processor for routing data packets including a MAC address, using a MAC address table stored in a writable memory. The switch further includes a second processor for routing data packets including an I... | 08/17/2010 |
| 7746871 | Method and apparatus for communicating data using TX/RX FIFO structure in a wideband stereo codec interface A method and interface are provided for using a memory that distinguishes transmission data from reception data and performs a First-In-First-Out (FIFO) operation on the transmission and reception data in a communication system. In the method, a controller receives ... | 06/29/2010 |
| 7733878 | System and method for packet transmission from fragmented buffer The present invention is directed to methods and systems for implementing a DMA scheduling mechanism and a DMA system for transmission from fragmented buffers. According to an aspect of the present invention, a processor controls several devices via a polled interfa... | 06/08/2010 |
| 7733879 | Memory management unit for a network switch A network switch having at least one port data port interface, a first memory, a second memory, and a memory management unit in connection with the at least one data port interface, the first memory, and the second memory. The memory management unit operates to rece... | 06/08/2010 |
| 7715410 | Queueing system for processors in packet routing operations In a data-packet processor, a configurable queuing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inser... | 05/11/2010 |
| 7715411 | Storage apparatus and data transfer method A controller controls exchange of data between a plurality of storage units based on transfer rates of the storage units and a fixed rate. If at least one of the transfer rates of a transfer-source storage unit and a transfer-destination storage unit are different t... | 05/11/2010 |
| 7672316 | Method for processing overhead of optical network and device thereof A method for overhead processing of optical network and device thereof are disclosed, the device includes: an overhead memory, an overhead processor, and an overhead processor control module. The overhead processor control module is used for controlling the operatio... | 03/02/2010 |
| 7672315 | Methods and apparatus for deskewing VCAT/LCAS members Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans th... | 03/02/2010 |
| 7626990 | Packet counters and packet adders for traffic profiling in a multiprocessor router A packet counter/adder for use in a multiprocessor system. The packet counter stores a counter value of data packets processed by a plurality of processors in the multiprocessor system. The packet counter comprises a first register capable of storing the counter val... | 12/01/2009 |
| 7620057 | Cache line replacement with zero latency A method for cache management includes assigning a respective cache line in a cache of a processing device to each of a plurality of processing flows in the processing device, and loading respective context data relating to each of the processing flows from a memory... | 11/17/2009 |
| 7551626 | Queueing system for processors in packet routing operations In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inse... | 06/23/2009 |
| 7529252 | Weighted queuing scheme for managing datagrams within a network device using single port double buffer (ping-pong) memory A method of handling data in a memory of a network device is disclosed. The method includes the steps of storing portions of a datagram, being handled by a network device, in a memory, where the memory comprises two logic memory blocks, storing at least two pointers... | 05/05/2009 |
| 7512135 | Method for transferring data among a logical layer, physical layer, and storage device Provided is a method for transferring data among a logical layer, physical layer, and storage device. The logical layer allocates a buffer to use to write data to a storage device. The physical layer manages access to the storage device. The logical layer determines... | 03/31/2009 |
| 7499457 | Method and apparatus for enforcing packet destination specific priority using threads A method for processing a plurality of packets that includes receiving the plurality of packets from a network, analyzing each of the plurality of packets by a classifier to determine to which of a plurality of temporary data structures each of the plurality of pack... | 03/03/2009 |
| 7460545 | Enhanced SDRAM bandwidth usage and memory management for TDM traffic A method and apparatus for managing memory for time division multiplexed high speed data traffic is provided. The method and apparatus utilize an interleaving approach in association with multiple memory banks, such as within SDRAM, to perform highly efficient data ... | 12/02/2008 |
| 7443863 | Cell switching method and system A cell switching method and system are disclosed that divide an input ATM cell into ATM adaptation layer (AAL) 2-type common part sublayer (CPS) packets. The divided CPS packets are stored in different first storage areas, in accordance with virtual paths/virtual ch... | 10/28/2008 |
| 7423981 | Method and apparatus for an incremental update of a longest prefix match lookup table A method and apparatus for performing an incremental update of a lookup table while the lookup table is available for searching is presented. To add or delete a route, a second set of routes is stored in a second memory space in the lookup table, while access is pro... | 09/09/2008 |
| 7420977 | Method and apparatus of inter-chip bus shared by message passing and memory access A system of switches having a memory/command bus having a first interface, a second interface and a third interface. A memory is connected to the third interface of the memory/command bus. The memory has a first memory address. A first switch monitors the memory/com... | 09/02/2008 |
| 7417986 | Shared buffer switch interface A system and method for using a single shared buffer to service multiple destinations for a telecommunications switch is disclosed. Upon receiving a cell of data to be sent to a destination, an interface stores the cell in a shared buffer. The address of the cell in... | 08/26/2008 |
| 7411949 | System, method and apparatus for preparing a table for a cell scheduler Methods, apparatuses and systems for populating a data structure. The data structure may be established in a memory unit and may have a total number of N slots for entries. In this case, N is defined as an integer representing the total number of slots in the data s... | 08/12/2008 |
| 7403976 | Method and apparatus for reducing pool starvation in a shared memory switch A switch includes a reserved pool of buffers in a shared memory. The reserved pool of buffers is reserved for exclusive use by an egress port. The switch includes pool select logic which selects a free buffer from the reserved pool for storing data received from an ... | 07/22/2008 |
| 7391766 | Packet unstopper system for a parallel packet switch A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ... | 06/24/2008 |
| 7366179 | Dual-PHY based integrated access device A dual PHY-based integrated access device (IAD) platform employs a highly integrated time division multiplexed (TDM), a synchronous transfer mode (ATM) cell based architecture, to provide enhanced interfacing flexibility for multiple and diverse signaling protocols,... | 04/29/2008 |
| 7366865 | Enqueueing entries in a packet queue referencing packets Provided are a method, system, network processor, network device, and article of manufacture for enqueueing entries in a packet queue referencing packets. When adding a packet to a first memory area, an entry is written to a packet queue in a second memory area refe... | 04/29/2008 |
| 7360153 | Method and apparatus for importing digital switching system data into a spreadsheet program A method and apparatus for importing digital switching system data into a spreadsheet program. Via the switch data examiner of the present invention, raw data from a digital switch/switching system such as the 5ESS® is converted by the switch data examiner to a for... | 04/15/2008 |
| 7359403 | Data segmentation method in a telecommunications system In a telecommunications system a larger higher layer data unit (SDU) is segmented into smaller segments on the lower layer (RLC). A segmentation length information is used to indicate the lengths of the segments in a lower layer protocol data unit (PDU). Specific va... | 04/15/2008 |
| 7356624 | Interface between different clock rate components A circuit for interfacing between a first component 11 operating at a first clock rate and a second component 12 operating at a second clock rate, wherein the second clock rate is higher than the first clock rate. The circuit comprises a first buffer | 04/08/2008 |
| 7353329 | Memory buffer device integrating refresh logic Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memo... | 04/01/2008 |
| 7353332 | Switching circuit implementing variable string matching A content matching engine (CME) uses a content addressable memory (CAM) array that stores a plurality of strings in separate entries. The strings define one or more rules to be matched. The strings of each rule are linked, thereby providing a required order. The str... | 04/01/2008 |
