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| Number | Title | Issue Date |
| 8179901 | System and method for squelching a recovered clock in an ethernet network A system and method for squelching a recovered clock in an Ethernet network. In one embodiment the invention provides a method for squelching a recovered clock in an Ethernet network comprising a local node coupled to a remote node by a link, the method including re... | 05/15/2012 |
| 8116321 | System and method for routing asynchronous signals A router, for routing at least one input signal to at least one output, comprises at least one input module and at least one output module. Each of the input and output modules includes at least one clock selector circuit for selecting from among a first and second ... | 02/14/2012 |
| 8116322 | Method and apparatus for controlling reporting of an event timestamp The present invention discloses a method for controlling the reporting of an event timestamp. The method includes the following steps: a timestamp control parameter is set; the MG determines whether to report the timestamp of the event according to the timestamp con... | 02/14/2012 |
| 8081639 | Method and apparatus for supporting client data transport with timing transparency Clock recovery is used in a variety of communications network applications to enable nodes using different clocks to operate in an effectively synchronized manner. Example embodiments of the present invention include an apparatus and corresponding method for support... | 12/20/2011 |
| 8018950 | Systems and methods for distributing GPS clock to communications devices A method for synchronizing network elements to a global clock derived from the GPS clock acquired by a plurality of base stations. The global clock is distributed to controllers of various networks, and from there to network access devices. The network access device... | 09/13/2011 |
| 7912073 | Synchronizing multiple data converters Synchronizing multiple-phase data converters by exchanging terminal count pulses via a bidirectional link. Multiple-phase data converters such as analog to digital converters (ADCs) or digital to analog converters (DACs) are synchronized to operate at the same phase... | 03/22/2011 |
| 7843946 | Method and system for providing via a data network information data for recovering a clock frequency At an ingress interface of a data network first information data are generated, at an egress interface of the data network second information data are generated, correction data are generated on the basis of the second information data, and at the egress interface a... | 11/30/2010 |
| 7835366 | Three-way message exchange clock synchronization The invention includes a technique for clock recovery in a network having master and slave clocks in respective Time Division Multiplexing (“TDM”) network segments which are interconnected by a non-TDM segment. Master clock timestamps are sent to the slave. The ... | 11/16/2010 |
| 7826460 | Network-on-chip apparatus, and method for controlling dynamic frequency for the same A network-on-chip apparatus including a plurality of network interfaces being independently connected to a plurality of processing elements; a network including a plurality of switches for controlling data transmission/reception between the network interfaces; and a... | 11/02/2010 |
| 7778252 | Hardware monitor of LIN time budget Local Interconnect Network message budget calculation error is reduced by utilizing an eight bit time measurement of the sync byte in the message header. The method determines the header budget separately from the data budget, simplifying the required logic. The syn... | 08/17/2010 |
| 7773606 | Timing distribution within a network element while supporting multiple timing domains According to one embodiment of the invention, a network element synchronizes a number of clocks within the system while supporting multiple independent timing domains. The network element includes a local clock, which is free-running and is not necessarily synchroni... | 08/10/2010 |
| 7720077 | Timed packet processing to regulate data transfer between components of a gateway for a constant delay network In one embodiment, a gateway for a constant delay network identifies a baseband clock that is synchronized by exchanging synchronization messages over a packet switched network. The gateway then generates a strobe by manipulating the identified baseband clock using ... | 05/18/2010 |
| 7710981 | Apparatus for and method of generating a time reference In one embodiment, a system is configured to generate a time reference where the system includes a bi-directional loop configured to have a first propagation speed in a first direction and a second propagation speed in a second direction, wherein the first propagati... | 05/04/2010 |
| 7697546 | Synchronization of distributed cable modem network components A distributed cable modem termination system of the present invention includes a downstream transmitter hub, an upstream receiver hub, and a head end that communicatively couples to the downstream transmitter hub and to the upstream receiver hub via a packet data ne... | 04/13/2010 |
| 7684413 | System and method for rate agile adaptive clocking in a packet-based network A system for transmitting a clock signal through a packet-based network is disclosed. The system comprises a first node configured to measure a clock frequency of the clock signal and calculate an accuracy indicator of the measured clock frequency; a second node con... | 03/23/2010 |
| 7664118 | System and method for high precision clock recovery over packet networks An innovative system and method for achieving high precision clock recovery, i.e. reconstruction of the clock signal having the same frequency, over a packet switched network. The proposed method utilizes a minimum network delay approach, which overcomes the problem... | 02/16/2010 |
| 7630383 | Synchronization of time stamps of peer devices in a communication node Networks and methods are disclosed for synchronizing time stamps of peer devices. In one embodiment, a first communication node comprised of peer devices is connected to a second communication node. The first and second communication nodes communicate according to a... | 12/08/2009 |
| 7561582 | Data reception device A data reception device having a reception data buffer unit storing a plurality of packets contained in a data packet, a reception data amount measuring unit measuring the data amount stored in the reception data buffer unit, a variable clock generation unit generat... | 07/14/2009 |
| 7558275 | System and method for clock replication using reference clock Data encoded with a video clock is transmitted over a communication link in accordance with a communication reference signal, which in one embodiment is a wireless link. In one embodiment, the video clock is independent from the communication reference signal. The c... | 07/07/2009 |
| 7539200 | Line-timing in packet-based networks In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal fro... | 05/26/2009 |
| 7450593 | Clock difference compensation for a network A method and apparatus to perform clock compensation for a jitter buffer are described. ... | 11/11/2008 |
| 7444168 | Radio communication semiconductor integrated circuit, data processing semiconductor integrated circuit and portable device A portable device having a communication function composed of a plurality of LSIs operated in synchronization with a clock, such as a baseband LSI and a logic LSI such as an application processor, can synchronize the baseband LSI with the logic LSI without lowering ... | 10/28/2008 |
| 7430175 | Method and system for managing traffic in fibre channel systems Method and system for routing fiber channel frames using a fiber channel switch element is provided. The method includes, inserting a time stamp value in a fiber channel frame that is received at a receive segment of the fiber channel switch element; determining if ... | 09/30/2008 |
| 7426194 | System and method for asynchronous wireless services using reverse service schema generation A notification service and correspondingly configured wireless device for providing asynchronous communications over a communication network for an application of the wireless device in communication with a selected service. The selected service has a source schema ... | 09/16/2008 |
| 7411970 | Adaptive clock recovery A method of recovering a clock signal for a TDM output from packets of TDM data which have been transmitted over a packet network, from a source having a source TDM clock to a destination having a destination TDM clock. The method includes providing at least some pa... | 08/12/2008 |
| 7408959 | Method and apparatus for ensuring cell ordering in large capacity switching systems and for synchronizing the arrival time of cells to a switch fabric Where links between a port module and plural switch fabric slices are of various lengths, a cell is transmitted from the port module to a switch fabric slice in response to a grant. The transmission is delayed by an amount based on a link round trip delay (RTD) valu... | 08/05/2008 |
| 7403507 | System and method for recovering system time in direct sequence spread spectrum communications A sleep control system and method are provided that permit a reference clock and the direct sequence spread spectrum (DSSS) modem in a mobile station receiver to be turned off and turned back on at arbitrary points in time while still maintaining accurate base stati... | 07/22/2008 |
| 7391837 | Newton's method-based timing recovery circuit A Newton's method-based timing recovery circuit is provided for to solving a polynomial accurately. The timing recovery circuit can generate an interpolation signal, whose timing errors are confined within a predetermined timing error range, which corresponds to a d... | 06/24/2008 |
| 7385990 | Method to improve the resolution of time measurements and alignment in packet networks by time modulation A method of recovering timing information in a packet network is disclosed wherein a modulation scheme is used to transport additional information required for clock recovery between the sender and receiver across the network. ... | 06/10/2008 |
| 7376120 | Radio base station synchronizing responsive to conditions being met In the case of radio base stations of different kinds, a synchronization in a radio section cannot be established so that the efficiently effective use of electric waves cannot be retained. According to the invention, therefore, there is provided a TDMA type mobile ... | 05/20/2008 |
| 7372819 | Adaptive packet routing A method of determining the latency of a route in a packet-switched network, a packet switch for use in such a method and network and a packet-switched network are disclosed. Preferably, each switch maintains a routing table that records the latency of the routes ac... | 05/13/2008 |
| 7369491 | Regulating data-burst transfer The invention discloses methods and apparatus for regulating the transfer of data bursts across a data network comprising electronic edge nodes interconnected by fast-switching optical core nodes. To facilitate switching at an electronic edge node, data bursts are o... | 05/06/2008 |
| 7362767 | Integrated circuit with on-chip clock frequency matching to upstream head end equipment One aspect of the present invention concerns a method for controlling the frequency of oscillation of a local clock signal comprising the steps of (A) generating the clock signal in response to a first control signal, (B) generating the first control signal in respo... | 04/22/2008 |
| 7356036 | Method providing distribution means for reference clocks across packetized networks Disclosed is a method of distributing a number of reference clocks across a packet network. The packet network has a master node and one or more slave nodes, the master node and each slave node having basis clocks. A sender sends time-stamped synchronization packets... | 04/08/2008 |
| 7352816 | Data oversampling via clock and data interpolation An oversampling delay is provided between clock and data signals by steering a current between first and second nodes. The first node is coupled to an input differential pair of a clock interpolator and a delayed differential pair of a data interpolator. The second ... | 04/01/2008 |
| 7353032 | Method, system, and apparatus for detecting a position of a terminal in a network A method, system, and apparatus are provided for detecting a position of a terminal in a network accurately without a GPS receiver. In one example, a method for locating a position of a terminal includes calculating a position of a base station; detecting a clock ti... | 04/01/2008 |
| 7352697 | Network processing using fractional time stamp values Fractional or fuzzy time stamp values are used during processing network traffic. Handling fractional time stamp values permits scaling down of time stamp values, so that fewer bits, and memory, are needed to store each fractional time stamp value. According to a sp... | 04/01/2008 |
| 7349409 | Receiver for the recovery of the clock in the transport of CBR services, originating both from DCTI transmitters and from SRTS transmitters A receiver provides for the recovery of the clock in the transport of CBR services originating both from DCTI transmitters and from SRTS transmitters over an ATM network, and comprises a generator of the control parameter, an oscillation system, a DCTI generator, a ... | 03/25/2008 |
| 7343510 | Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals A clock detection and selection circuit (100) can include a first counter (102-0) that generates a first count value CNT1 according to a first clock signal CLK1 and a second counter (102-1) that generates a second cou... | 03/11/2008 |
| 7336667 | Apparatus, method and program product to generate and use CRC in communications network The CRC for the CPS Header of an ATM AAL2 cell is generated by a CRC generator which uses the 8 bits of the CID field to generate partial 5 bits CRCs which are loaded in a first table. The 6 bits LI field and 5 bits UUI field are added to the partial 5 bits CRC to f... | 02/26/2008 |
