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| Number | Title | Issue Date |
| 8023363 | Time-to-digital converter apparatus A time-to-digital converter apparatus including a delay phase-locked loop, a subtracter, a multi-phase detector and a Vernier detector is disclosed. The delay phase-locked loop herein includes digital delay components for producing counting signals. The multi-phase ... | 09/20/2011 |
| 7986591 | Ultra high resolution timing measurement An integrated circuit for high-resolution timing measurement includes a delay pulse generator, the first oscillator to generate the first clock with the first frequency, the second oscillator to generate the second clock with the second frequency, an oscillator tune... | 07/26/2011 |
| 7843771 | High resolution time interpolator The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the e... | 11/30/2010 |
| 7460441 | Measuring a long time period A time period of an event is determined by charging a known value capacitor from a constant current source during the event. The resultant voltage on the capacitor is proportional to the event time period and may be calculated from the resultant voltage and known ca... | 12/02/2008 |
| 7423937 | Time converter A digital time converter with an embodiment including a coarse measuring circuit and a fine measuring circuit. The fine measuring circuit allows an accurate determination of the temporal position of an event inside a period of the time base, by interpolation or aver... | 09/09/2008 |
| 7400160 | Semiconductor integrated circuit device, measurement method therefore and measurement system for measuring AC characteristics thereof Disclosed is an AC characteristics measurement system that includes a flip-flop arranged in a loop of a ring oscillator; a clock generating circuit that receives a signal propagated in said loop of said ring oscillator and generates a clock signal to be supplied to ... | 07/15/2008 |
| 7379395 | Precise time measurement apparatus and method A time measurement system that uses two signals generated by direct digital synthesis. The generated signals have the same frequency but different phase. One signal is used to identify the start of the measurement interval and the other signal is used to identify a ... | 05/27/2008 |
| 7363556 | Testing apparatus and testing method A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory unit for storing the test result of said memory-under-test. The fail... | 04/22/2008 |
| 7330803 | High resolution time interval measurement apparatus and method A time interval measurement apparatus and method counts the total number of full clock time periods between two measurement signals. Clock fractional time periods are generated between each of the two measurement signals and the next leading edge of a full clock tim... | 02/12/2008 |
| 7327179 | Pulse generator, optical disk writer and tuner A pulse generator is provided for generating pulses with a selectable variable width and/or delay. The pulse generator comprises an oscillator and a selecting arrangement for selecting how many of a first group of delay elements are connected in series for delaying ... | 02/05/2008 |
| 7315489 | Method and apparatus for time measurement A method is provided for accurate time measurement. Time is first measured with a first oscillator. At designated intervals, a second oscillator is activated for a period of time based on the first oscillator. The second oscillator is more accurate than the first os... | 01/01/2008 |
| 7315270 | Differential delay-line analog-to-digital converter Differential delay-line analog-to-digital (A/D) converters for use in current and power sensing applications are provided. These A/D converters are well suited for a wide range of electronic applications, including over-load protection, current mode control, current... | 01/01/2008 |
| 7292044 | Integrating time measurement circuit for a channel of a test card In a first embodiment of the invention there is provided an electronic chip for use with an automatic testing equipment device testing a device under test. The device under test has a plurality of pins and the electronic chip is placed in a channel of a test card th... | 11/06/2007 |
| 7289578 | Wireless local area network apparatus A wireless local area network apparatus includes a transmitter and a receiver in which operation of the receiver is accurately synchronized with periodic signals from the transmitter. The periodic signals contain timing data indicating the state of a timer in the tr... | 10/30/2007 |
| 7280069 | Range-finding radar apparatus with high-resolution pulse-width calculation unit A radar apparatus includes a modulation signal generating unit that generates a modulation signal based on an internal clock with a cycle Tc and generates a trigger signal in synchronization with the modulation signal, a carrier wave generating unit that generates a... | 10/09/2007 |
| 7272078 | Efficient clock calibration in electronic equipment A representative measurement indicating a relative oscillation speed of a reference clock during a representative calibration period is ascertained. Multiple calibration periods are defined including first and second calibration periods. The first calibration period... | 09/18/2007 |
| 7269770 | AC coupled line testing using boundary scan test methodology An AC boundary scan cell is disclosed. For one embodiment the AC boundary scan cell includes a first multiplexer, a second multiplexer, a first data shift register, a second data register, an XOR logic gate, and a third multiplexer. For one such embodiment the AC bo... | 09/11/2007 |
| 7242257 | Calibration-associated systems and methods The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides an auto-calibration system. The system includes: a plurality of delay line elements (DLEs... | 07/10/2007 |
| 7219269 | Self-calibrating strobe signal generator A self-calibrating strobe signal generator for a BIST circuit responds to an edge of an input strobe signal by generating corresponding edges of first and second strobe signals separated in time by a target delay specified by input data. The strobe signal generator ... | 05/15/2007 |
| 7216047 | Time-delay discriminator A method of determining the delay between two corresponding noise-like signals comprises determining events at which the level of a first of the signal crosses a predetermined threshold, using each event to sample a second signal, combining the samples to produce an... | 05/08/2007 |
| 7212599 | Jitter and wander reduction apparatus The present invention is for an apparatus that receives input data at a non-uniform first data rate carried by a system clock, and provides output data at a substantially uniform second data rate that is nominally equal to the first data rate and is also carried by ... | 05/01/2007 |
| 7208934 | Apparatus for identification of locations of a circuit within an integrated circuit having low speed performance A test circuit for identification of locations with low speed performance. A grid of ring oscillator units and switches connect or disconnect the ring oscillator units to or from each other, such that the locations with low speed performance are identified according... | 04/24/2007 |
| 7184908 | Calibration method of time measurement apparatus There is provided a calibration method for a time measurement apparatus having a time-voltage converter for converting the time interval of measurement signals and clock signals to voltage, an analog-digital converter for converting this voltage to digital values, a... | 02/27/2007 |
| 7174521 | System and method for product yield prediction A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit ... | 02/06/2007 |
| 7133946 | Mechanism to repeat signals across an unrelated link According to one embodiment a system is disclosed. The system includes a first integrated circuit (IC) a first interface coupled to the first IC and a second IC coupled to the interface. The first IC transmits the state of each of a plurality of signals not associat... | 11/07/2006 |
| 7113886 | Circuit and method for distributing events in an event stream A circuit and related method for distributing events in an event stream (i.e., an electronic signal having a plurality of rising edge transitions and falling edge transitions). The circuit distributes the events in a primary event stream across multiple secondary ev... | 09/26/2006 |
| 7088155 | Clock generating circuit In a clock generation circuit generating a clock that is synchronized with a reference signal, it is an object to provide stable clocks by controlling phase jitter in a generated clock upon change of the reference signal, eliminate a stable-state phase difference be... | 08/08/2006 |
| 7085668 | Time measurement method using quadrature sine waves A time measurement circuit includes N time stamping units that each includes a dual sinusoid interpolator for achieving high timing resolution. The time measurement circuit is capable of time stamping input signals at a high re-trigger rate, and is thus well suited ... | 08/01/2006 |
| 7082175 | Method for controlled synchronization to an astable clock system, and reception unit corresponding thereto A method for controlled synchronization to an astable clock system, and reception unit corresponding thereto are disclosed. Soft synchronization using a slight change in the period duration of the clock signal produced makes it possible to alter said clock signal su... | 07/25/2006 |
| 7071751 | Counter-controlled delay line A counter-controlled delay line for delaying signals having a wide range of possible frequencies is described. The counter-controlled delay line receives an input clock and produces a delayed output clock based on a delay select control signal. The delay select cont... | 07/04/2006 |
| 7047179 | Clustered processors in an emulation engine Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit.... | 05/16/2006 |
| 7039471 | Method and device for calculating the steady-state time point of a controller A device for calculating the steady state behavior of a controller includes an amount generating unit for generating the amount of deviation of the regulator, a first threshold value calculation unit that detects whether the amount of deviation of the regulator has ... | 05/02/2006 |
| 7010058 | Wireless local area network apparatus A wireless local area network apparatus includes a transmitter and a receiver in which operation of the receiver is accurately synchronized with periodic signals from the transmitter. The periodic signals contain timing data indicating the state of a timer in the tr... | 03/07/2006 |
| 6996032 | BIST circuit for measuring path delay in an IC A BIST circuit for an IC measures the time delay a rising or falling edge experiences as it passes through a signal path within the IC. A strobe circuit within the BIST circuit generates edges in two signals A and B in delayed response to edges of a STROBE signal. A... | 02/07/2006 |
| 6978229 | Efficient method for modeling and simulation of the impact of local and global variation on integrated circuits A computer implemented method for statistical modeling and simulation of the impact of global variation and local mismatch on the performance of integrated circuits, comprises the steps of: estimating a representation of component mismatch from device performance me... | 12/20/2005 |
| 6965648 | Source synchronous link integrity validation A system may perform interconnect BIST (IBIST) testing on source synchronous links. The system may perform, at normal operating frequency, a source synchronous link test that tests a victim line on the source synchronous link using a transition weave pattern. The tr... | 11/15/2005 |
| 6950375 | Multi-phase clock time stamping Multi-phase clock time stamping for improving time stamp resolution is provided. One of many possible embodiments is a method for generating a time stamp having an improved time resolution for an event signal. Briefly described, one such method comprises the steps o... | 09/27/2005 |
| 6944810 | Method and apparatus for the testing of input/output drivers of a circuit In order to test the input and output drivers of a circuit, in particular an integrated semiconductor circuit, a method and apparatus is provided to connect the input or output drivers assigned to individual signal connections of the circuit to be tested in series t... | 09/13/2005 |
| 6944099 | Precise time period measurement Measurement of the period of a relatively slow but precise reference clock in terms of a high speed oscillating clock, such as from a voltage controlled oscillator (VCO). The reference clock is known to be accurate and stable and values of the time measurement unit ... | 09/13/2005 |
| 6943609 | Stratum clock state machine multiplexing switching A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out acti... | 09/13/2005 |
