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| Number | Title | Issue Date |
| 8125855 | User interface features for a watch A watch provides a chronographic function while the watch is in a “sport” mode. If a user activates a button relating to the chronographic function, such as a “start/lap” button, then the light for the watch will automatically activate. The light may remain ... | 02/28/2012 |
| 8064293 | High resolution time interpolator The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the e... | 11/22/2011 |
| 7903502 | Automatic read of current time when exiting low-power state utility A method and apparatus is described for computing a duration of a reduced power consumption state. A time of exiting from the reduced power consumption state is read prior to an execution of an interrupt routine. The read time of exiting is then stored in a register... | 03/08/2011 |
| 7898906 | User interface features for a watch A watch provides a chronographic function while the watch is in a “sport” mode. If a user activates a button relating to the chronographic function, such as a “start/lap” button, then the light for the watch will automatically activate. The light may remain ... | 03/01/2011 |
| 7508739 | Measurement system This invention relates to a measurement system for determining the running time that a person need to run over one of a plurality of selectable different out-and-back courses, departing from a common starting point that is the finish point at the same time, wherein ... | 03/24/2009 |
| 7400554 | Automatic read of current time when exiting low-power state A method and apparatus is described for computing a duration of a reduced power consumption state. A time of exiting from the reduced power consumption state is read prior to an execution of an interrupt routine. The read time of exiting is then stored in a register... | 07/15/2008 |
| 7394729 | Time constant based fixed parameter assignment A method for assigning a value to a fixed parameter in an electrical device where the fixed parameter has multiple states includes associating a time value to each state of the fixed parameter, driving a first input terminal of the electrical device to a first volta... | 07/01/2008 |
| 7372014 | Corrosion-proof pool deck connector system A poolside connector system and method for use with swimming pool race timing systems and signaling devices. A deck plate or similar poolside signal junction is provided with an optical receiver terminal, and a cable connection from a poolside signaling device such ... | 05/13/2008 |
| 7368967 | Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which... | 05/06/2008 |
| 7366966 | System and method for varying test signal durations and assert times for testing memory devices A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that inclu... | 04/29/2008 |
| 7362134 | Circuit and method for latch bypass A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypa... | 04/22/2008 |
| 7355387 | System and method for testing integrated circuit timing margins An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit includes circuitry for testing the timing margins of memory devices by determining the re... | 04/08/2008 |
| 7342848 | Lap timer The invention relates to an electronic timing device. The timing device has several modes including Basic mode and Lap mode. Additionally, the timing device computes the speed of an item being timed. Further, the outside of the device is designed to display informat... | 03/11/2008 |
| 7339853 | Time stamping events for fractions of a clock cycle Generally, the embodiments are directed to circuits and methods for time stamping an event at a fraction of a clock cycle. A time stamping circuit comprises two or more detection circuits. The detection circuits receive an event-in signal and generate event signals ... | 03/04/2008 |
| 7331706 | Zero-resetting device for two time counters This device for the simultaneous zero-resetting of two counters, the pivot axes of which are fixedly connected to respective heart-shaped zero-resetting cams (7, 8), comprises a zero-resetting lever (2) containing two hammers (6c, 6 | 02/19/2008 |
| 7333725 | Method and apparatus for metadata synchronization A method and apparatus provides for accurately synchronizing a plurality of sensors, as well as for providing accurate timing information (e.g. timing metadata) associated with the synchronized data capture. According to one aspect of the invention, an apparatus inc... | 02/19/2008 |
| 7330803 | High resolution time interval measurement apparatus and method A time interval measurement apparatus and method counts the total number of full clock time periods between two measurement signals. Clock fractional time periods are generated between each of the two measurement signals and the next leading edge of a full clock tim... | 02/12/2008 |
| 7328381 | Testing system and method for memory modules having a memory hub architecture A testing method and system is used to test memory modules each of which has a memory hub coupled to a plurality of memory devices. The testing system and method includes a test interface circuit having a memory interface that is coupled to transmit and receive memo... | 02/05/2008 |
| 7321945 | Interrupt control device sending data to a processor at an optimized time An interrupt control device for issuing interrupts to a central processing unit (CPU) includes an object acquiring unit for acquiring data or resource(s) for use by the CPU and an interrupt issuing unit for issuing interrupts to the CPU. The interrupt issuing unit i... | 01/22/2008 |
| 7319340 | Integrated circuit load board and method having on-board test circuit An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit generates test signals that are applied to the integrated circuit sockets. The integrated... | 01/15/2008 |
| 7317343 | Pulse-generation circuit with multi-delay block and set-reset latches In one embodiment of the invention, a pulse-generation circuit for generating control signals has clock-delay circuitry for generating a plurality of differently delayed clock signals. Each control signal is generated by a set-reset latch that receives its set and r... | 01/08/2008 |
| 7315489 | Method and apparatus for time measurement A method is provided for accurate time measurement. Time is first measured with a first oscillator. At designated intervals, a second oscillator is activated for a period of time based on the first oscillator. The second oscillator is more accurate than the first os... | 01/01/2008 |
| 7315270 | Differential delay-line analog-to-digital converter Differential delay-line analog-to-digital (A/D) converters for use in current and power sensing applications are provided. These A/D converters are well suited for a wide range of electronic applications, including over-load protection, current mode control, current... | 01/01/2008 |
| 7305599 | Testing propagation delay of a shift register using a ring oscillator Testing signal propagation delay of a shift register circuit is described. A ring oscillator has a first sequential element, a second sequential element, and a shift register circuit. The shift register circuit is coupled in series between the first sequential eleme... | 12/04/2007 |
| 7294998 | Timing generation circuit and semiconductor test device having the timing generation circuit A timing generation circuit can increase a maximum delay amount without changing the configuration of a timing memory. The timing generation circuit includes: a timing memory (TMM) 10 containing predetermined timing data; a plurality of down counters 20 | 11/13/2007 |
| 7278290 | Projectile impact energy and location measurement system A projectile impact energy and location measurement system is taught employing a target apparatus having an impact plate of a solid durable substance such as steel or titanium. Disposed over the plate is a layer of elastoluminescent material composed of zinc sulfide... | 10/09/2007 |
| 7275859 | Display device for watch The invention concerns a display device for a watch movement comprising: a frame (110), an assembly of wheels pivotably mounted on the frame and wherein the angular position of a first (116) and a second (120) among them is based on the state of... | 10/02/2007 |
| 7263149 | Apparatus and method for generating a distributed clock signal The present invention provides a method and apparatus for synchronizing signal transfers between two clock domains, where the clock domains have a gear ratio relationship. A gear ratio means that the clocks are related by a ratio, such that each clock has a differen... | 08/28/2007 |
| 7260754 | Semiconductor device with speed binning test circuit and test method thereof A speed binning test circuit for a semiconductor device may include a plurality of circuit groups arranged along a boundary of a chip circuit. Each circuit group may include a different number of unit delay circuits that may form a chain structure. The speed binning... | 08/21/2007 |
| 7228476 | System and method for testing integrated circuits at operational speed using high-frequency clock converter A system tests an integrated circuit at operational speed. The system includes a high frequency clock converter that receives test clock signals at a speed lower than operational speed of the integrated circuit to be tested. The high frequency clock converter genera... | 06/05/2007 |
| 7221724 | Precision timing generation A precision timing generator and an associate method provide a precise clock signal based on a reference clock signal. Using the reference clock signal in a phase locked loop or delay locked loop, a number of clock signals of equal frequency are generated separated ... | 05/22/2007 |
| 7216047 | Time-delay discriminator A method of determining the delay between two corresponding noise-like signals comprises determining events at which the level of a first of the signal crosses a predetermined threshold, using each event to sample a second signal, combining the samples to produce an... | 05/08/2007 |
| 7212939 | Method and system for timing measurement of embedded macro module A method and system is presented for measuring a data access time of an embedded macro module in an integrated circuit. A single external test signal is inputted into the embedded macro module for enabling a data input therein and extracting a data output therefrom.... | 05/01/2007 |
| 7209065 | Rotary flash ADC A system and method for converting an analog signal to a digital signal is disclosed. The system includes a multiphase oscillator preferable a rotary oscillator, a sample and hold circuit, an integrator and a time-to-digital converter. The multiphase oscillator has ... | 04/24/2007 |
| 7190639 | Method and apparatus for measuring fluid viscosity using electric conductance An apparatus uses electrical conductance to determine the start and stop times for viscosity measurements using efflux cups. An efflux cup and two probes are immersed and removed from the fluid. An electric current is applied between each probe and the efflux cup. A... | 03/13/2007 |
| 7184470 | Method and apparatus for measurement of jitter A method and circuit for measurement of jitter in which a reference clock (404) runs at a frequency offset to the incoming signal (I) so that the phase of the two clocks drift over time, enabling detection of jitter in the input signal by measurement of the d... | 02/27/2007 |
| 7170826 | Multifunctional watch There is provided a multifunction timepiece wherein the visibility of pointers can be improved, and increases in the thickness of the timepiece can be reduced. This timepiece includes a dial, an hour hand, a minute hand, a pointer, and a movement. The dial has a dia... | 01/30/2007 |
| 7171601 | Programmable jitter generator A jitter generator produces a jittery test signal for use in performing a jitter test on an integrated circuit (IC) device under test (DUT). The jitter generator includes a programmable delay circuit for delaying a non-jittery input signal with a varying delay contr... | 01/30/2007 |
| 7167419 | Beverage brewer timer A timer is provided for indicating when a beverage within a beverage container is no longer fresh. The timer includes a timer body and a clip. The timer body contains electronic circuitry adapted to display a time remaining before the beverage is no longer fresh. Th... | 01/23/2007 |
| 7151367 | Method of measuring duty cycle A method for measuring the duty cycle of a signal. The method is fast enough to allow duty cycle measurements of semi-conductor components during production. The method can also be performed inexpensively using automatic test equipment. A comparator in a digital cha... | 12/19/2006 |
