Did You Know...
...that when IBM conducted a market study of Chester Carlson's invention in 1959, the company concluded that it would take only 5000 units of his new product to saturate the market? IBM therefore declined to be part of the new product introduction. Too bad for IBM. Carlson's invention was the xerography process, and his new product was the beginning of the Xerox Corporation. It is estimated that every day, worldwide, 3,000,000,000 copies are made!!
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| Number | Title | Issue Date |
| 6587394 | Programmable address logic for solid state diode-based memory A level of a solid state memory device includes main memory and address logic. The address logic includes first and second groups of address elements. Current-carrying capability of the first group of address elements is greater than current-carrying capa... | 07/01/2003 |
| 6577551 | Semiconductor integrated circuit having a built-in data storage circuit for nonvolatile storage of control data A semiconductor integrated circuit includes a control data storage circuit (6) having nonvolatile storage devices with programmed control data and a latch circuit for holding data read out from the storage devices, and a read control circuit (7) for contr... | 06/10/2003 |
| 6570798 | Antifuse memory cell and antifuse memory cell array An antifuse memory cell comprises a first antifuse having a first electrode and a second electrode, a second antifuse having a first electrode and a second electrode, and an MOS transistor having a gate, a source and a drain, wherein the first electrode o... | 05/27/2003 |
| 6570805 | Antifuse memory cell and antifuse memory cell array An antifuse memory cell comprises a first antifuse having a first electrode and a second electrode, a second antifuse having a first electrode and a second electrode, and an MOS transistor having a gate, a source and a drain, wherein the first electrode o... | 05/27/2003 |
| 6545926 | Antifuse address detecting circuit programmable by applying a high voltage and semiconductor integrated circuit device provided with the same An input protective circuit in a semiconductor integrated circuit device includes a bipolar transistor arranged for an interconnection layer. An N-type active region in the bipolar transistor is connected to an electrode of a program element. The electrod... | 04/08/2003 |
| 6545898 | Method and apparatus for writing memory arrays using external source of high programming voltage A passive element memory array preferably biases selected X-lines to an externally received VPP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to VPP minus a first offset voltage, and unselected X-li... | 04/08/2003 |
| 6545928 | Antifuse programming current limiter Methods for enhancing the programming of antifuses are discussed. The methods include accessing an antifuse in an antifuse bank by providing an address, raising a signal source to a high voltage level for programming the antifuse, sensing current flowing ... | 04/08/2003 |
| 6541290 | Architecture of laser fuse box of semiconductor integrated circuit and method for fabricating the same A fuse layout structure in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same. In one embodiment of the invention, the fuse layout structure in a laser fuse box of the semiconductor integrated circuit comprises a ... | 04/01/2003 |
| 6535418 | Optically programmable address logic for solid state diode-based memory A level of a solid state memory device includes main memory and address logic. The address logic is programmed by causing current to flow through an address element of the logic; and irradiating the address element so that the address element changes resi... | 03/18/2003 |
| 6525955 | Memory cell with fuse element The present invention relates to a one-time programmable memory cell and a method of setting a state for a one-time programmable memory cell. The memory cell includes a storage element adapted to store data and two thin gated fuses coupled to the storage ... | 02/25/2003 |
| 6496423 | Chip ID register configuration A chip ID register configuration includes a shift register having individual stages. A fuse device connected to the shift register has fuses each substantially assigned to a respective one of the individual stages of the shift register, for identifying a ... | 12/17/2002 |
| 6490219 | Semiconductor integrated circuit device and method of manufacturing thereof A semiconductor integrated circuit device comprises an integrated circuit portion, a fuse element block, and a data transfer selecting circuit. The fuse element block includes a programmable fuse element. The data transfer selecting circuit selects one of... | 12/03/2002 |
| 6483734 | Memory device having memory cells capable of four states A memory device includes memory cells having a re-writeable element and a write-once element in series with the re-writeable element. The re-writeable element is programmable between a high resistance state and a low resistance state. The write-once eleme... | 11/19/2002 |
| 6448626 | Semiconductor memory device having a plurality of laser fuses A semiconductor memory device having a plurality of laser fuses is provided. In the semiconductor memory device, the plurality of laser fuses include a first region including the ends of one side of the plurality of laser fuses, a second region including ... | 09/10/2002 |
| 6445606 | Secure poly fuse ROM with a power-on or on-reset hardware security features and method therefor A secure one-time programmable (OTP) salicided poly fuse array (2×8) cells with a power-on or on-reset hardware security feature is proposed. The secure OTP which is based on a primitive building cell that includes a salicided poly fuse and a MOS switch,... | 09/03/2002 |
| 6445605 | Circuit for programming antifuse bits A method of verifying whether unprogrammed antifuses are leaky in a semiconductor memory. The method involves the steps of: connecting the antifuse in series with a node; providing current to the node, the current being sufficient to charge the node from ... | 09/03/2002 |
| 6442063 | Integrated memory having memory cells with magnetoresistive memory effect The integrated memory has memory cells with a magnetoresistive memory effect connected to column lines and row lines. Each of the memory cells is respectively wired between one of the column lines and one of the row lines. They are constructed such that t... | 08/27/2002 |
| 6433405 | Integrated circuit having provisions for remote storage of chip specific operating parameters An integrated circuit having programmable fuse provisions separate from critical circuitry, for storing chip specific operational information necessary for proper integrated circuit operation. These separate provisions include a fuse block which contains ... | 08/13/2002 |
| 6400632 | Semiconductor device including a fuse circuit in which the electric current is cut off after blowing so as to prevent voltage fall The antifuse is brought into an electrically conducted state by setting the voltage Vpgm to a high voltage after activating the signal SA and setting the node N1 once to an L-level. By inversion of the latch, the voltage of the node N1 will be the power s... | 06/04/2002 |
| 6373772 | Semiconductor integrated circuit device having fuses and fuse latch circuits A semiconductor integrated circuit device has a semiconductor integrated circuit with first layout sections where fuses are laid out and second layout sections where fuse latch circuits, which correspond to the fuses, are laid out. The first layout sectio... | 04/16/2002 |
| 6344679 | Diode with alterable conductivity and method of making same A semiconductor device (102) having a plurality of diodes (100) with alterable electrical conductivity by a source of energy (30), e.g., a laser, external to the semiconductor device. The diodes are formed and energy is applied to alter the electrical con... | 02/05/2002 |
| 6339559 | Decode scheme for programming antifuses arranged in banks Described is an antifuse array comprising a plurality of antifuse elements and a plurality of cell plates. Each of the antifuse elements comprises a programming transistor and one of the cell plates. The programming transistor and the cell plate of each a... | 01/15/2002 |
| 6307423 | Programmable circuit with preview function A programmable circuit and method of programming that provide an easily fabricated circuit that does not require specialize manufacturing or packaging techniques. The circuit provides for temporarily setting the circuit outputs which can then be used for ... | 10/23/2001 |
| 6292422 | Read/write protected electrical fuse A system and method is provided for storing a data value by implementation of electrical fuses. Typically, the electrical fuses are provided in a fuse array broken up into a plurality of fuse chains addressable by a control logic circuit. The control logi... | 09/18/2001 |
| 6274410 | Method of programming a semiconductor memory A method of programming a semiconductor memory includes forming a multiplicity of fuse links in at least two mutually parallel planes in a semiconductor body, and separating the fuse links from one another with an electrical insulator. It also includes ir... | 08/14/2001 |
| 6268760 | Hysteretic fuse control circuit with serial interface fusing A fuse status detection and serial interface programming circuit which provides a current-free method of detecting a fused/non-fused state of a fuse, and which also prevents filament regrowth. The circuit employs an output inverter to monitor the status o... | 07/31/2001 |
| 6266269 | Three terminal non-volatile memory element A three terminal non-volatile memory element includes a standard (low voltage) CMOS transistor, i.e. a storage transistor, having a drain coupled to a read bit line and a source connected to ground. The storage transistor is programmed by applying a high ... | 07/24/2001 |
| 6263295 | Programmable voltage divider and method for testing the impedance of a programmable element A programmable voltage divider has normal and test modes of operation. The divider includes first and second supply nodes, a divider node that provides a data value, and a first divider element that is coupled between the first supply node and the divider... | 07/17/2001 |
| 6259147 | Semiconductor device having a fuse layer A semiconductor device includes: an insulation layer; a fuse layer extending on the insulation layer in one direction and disconnected through light radiation to control a redundant circuit; a pseudo fuse layer on the insulation layer along at least one s... | 07/10/2001 |
| 6256239 | Redundant decision circuit for semiconductor memory device A redundancy decision circuit for specifying a redundant memory cell in a memory cell array when a normal cell is defective. The circuit includes a switching element, a fuse and a load circuit connected in series between high and low potential supplies. A... | 07/03/2001 |
| 6240033 | Antifuse circuitry for post-package DRAM repair The anti-fuse circuit includes three sub-blocks: a multiplexer having inputs of control signals and addresses and yielding the activation of a programming signal and program addresses; a programming voltage generator consisting of an oscillator and a char... | 05/29/2001 |
| 6233185 | Wafer level burn-in of memory integrated circuits A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitor... | 05/15/2001 |
| 6229733 | Non-volatile memory cell for linear mos integrated circuits utilizing fused mosfet gate oxide A non-volatile memory cell comprising a metal oxide semiconductor field effect transistor (MOSFET) fabricated to read back a logic level "one" state and programmable by a gate to drain fusing to read back to a logic level "zero" state. The drain is patter... | 05/08/2001 |
| 6208549 | One-time programmable poly-fuse circuit for implementing non-volatile functions in a standard sub 0.35 micron CMOS A memory system is provided for accessing an array of polycide fuses. The memory system includes an access control circuit configured to individually program and read each of the polycide fuses in the array. Row and column decoding circuitry is provided t... | 03/27/2001 |
| 6205050 | Programmed circuit in a semiconductor device A semiconductor memory device has a redundancy decoder for replacing a defective memory cell by a redundancy memory cell. The redundancy decoder includes a programmed flip-flop having first and second transistors. The load of the first transistor is imple... | 03/20/2001 |
| 6194738 | Method and apparatus for storage of test results within an integrated circuit An integrated circuit memory device has a plurality of nonvolatile programmable elements which are used to store a pass/fail status bit at selected milestones in a test sequence. At selected points in the test process an element may be programmed to indic... | 02/27/2001 |
| 6181627 | Antifuse detection circuit An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two anti... | 01/30/2001 |
| 6172896 | Layout arrangements of fuse boxes for integrated circuit devices, including bent and straight fuses An integrated circuit device such as an integrated circuit memory device, includes a first fuse group such as a first laser fuse group including a plurality of first laser fuses each having a first narrow end, a second opposite end which is wider and a be... | 01/09/2001 |
| 6163488 | Semiconductor device with antifuse In a DRAM with an antifuse for programming a defective address, the antifuse and one electrode of a capacitor are connected to a shared node and the other electrode of the capacitor receives a boost signal. To blow the antifuse, the shared node is set hig... | 12/19/2000 |
| 6154398 | Low current redundancy anti-fuse method and apparatus A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programme... | 11/28/2000 |
