Famous Patents
The first match was accidentally discovered in 1826 when John Walker scraped a stick with chemicals on the end against a stone floor.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8179708 | Anti-cross-talk circuitry for ROM arrays A circuit and method precharge a selected bit-line in a read only memory (ROM) array during a precharge period of a read cycle. At least one bit-line adjacent to the selected bit-line is discharged during the precharge period. After the precharge period, the selecte... | 05/15/2012 |
| 8154902 | Bit line decoder architecture for NOR-type memory array An integrated circuit including a plurality of bit lines, a memory array, and a bit line decoder. The memory array includes a plurality of memory cells, wherein each memory cell is respectively coupled to (i) two corresponding bit lines of the plurality of bit lines... | 04/10/2012 |
| 8089798 | Method for operating one-time programmable read-only memory A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherei... | 01/03/2012 |
| 8085570 | Memory A memory includes conductive layers provided to extend along the word lines, memory cells each including a diode having a cathode connected to the conductive layer and a source line reading data stored in the memory cells, wherein either the conductive layers or the... | 12/27/2011 |
| 8050075 | Memory A memory is so formed that, in a first block and a second block each including a prescribed number of the bit lines arranged therein, positions of the bit lines simultaneously selected in the first and second blocks with reference to ends of the first and second blo... | 11/01/2011 |
| 8050076 | One-time programmable memory cell with shiftable threshold voltage transistor According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable t... | 11/01/2011 |
| 7995368 | Memory cell architecture Embodiments of the present invention disclose a memory architecture for optimizing memory performance and size. Memory optimization is realized by configuring the memory to a particular logic state; that is, restricting memory data storage to either logic ā0ā or... | 08/09/2011 |
| 7940545 | Low power read scheme for read only memory (ROM) A ROM includes a ROM array, an address decoder, a control circuit, a precharge tracker, a precharge circuit, a reference word line, a reference bit line and a reference sense generator. The control circuit generates control signals for reading the ROM. The address d... | 05/10/2011 |
| 7936581 | Bit line decoder architecture for nor-type memory array A bit line decoder for sensing states of memory cells of a memory array includes D control devices that selectively communicate with (Dā1) bit lines of the memory array. (Dā2) of the D control devices are arranged in a first level and two of the D control device... | 05/03/2011 |
| 7929330 | Multi-bit memory device using multi-plug A memory device may include a cathode, an anode, a link connected to the anode, and a first connection element that connects the link to the cathode. The link and the anode may be located in a position lower than that of the cathode or the link and the anode may be ... | 04/19/2011 |
| 7903444 | One-time programmable memory and operating method thereof A one-time programmable memory cell is provided, the one-time programmable memory cell comprises: a gate dielectric layer disposed on a well; a gate electrode disposed on the gate dielectric layer; source/drain regions disposed in the well at the sides of the gate e... | 03/08/2011 |
| 7869246 | Bit line decoder architecture for NOR-type memory array A bit line decoder includes control devices that selectively communicate with bit lines and that are arranged in a multi-level configuration having a plurality of levels. Each of the levels includes a plurality of the control devices connected to each other in serie... | 01/11/2011 |
| 7869247 | Bit line decoder architecture for NOR-type memory array A bit line decoder for sensing states of memory cells of a memory array includes a first sub-decoder that (i) is adjacent to the memory array and (ii) includes D control devices arranged in a first of two levels of the bit line decoder. The D control devices selecti... | 01/11/2011 |
| 7869248 | Bit line decoder architecture for NOR-type memory array A bit line decoder for sensing states of memory cells of a memory array includes R first sub-decoders that communicate with R memory sub-arrays of the memory array, respectively, where R is an integer greater than 1. Each of the R first sub-decoders includes D contr... | 01/11/2011 |
| 7864557 | Flexible OTP sector protection architecture for flash memories A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plural... | 01/04/2011 |
| 7852656 | One-time programmable cell and memory device having the same One-time programmable cell and memory device having the same includes a first metal oxide semiconductor (MOS) transistor configured to form a current path between a first node and a second node in response to a read-control signal, a second MOS transistor configured... | 12/14/2010 |
| 7738305 | Read-out circuit for or in a ROM memory; ROM memory and method for reading the ROM memory A read-out circuit for or in a ROM memory, comprises an input, a comparator circuit, a threshold setting, and a control signal generator for driving the threshold setting generator. A read signal can be coupled into the input. The read signal, depending on the infor... | 06/15/2010 |
| 7729155 | High speed, low power, low leakage read only memory A read only memory (ROM) for providing a high operational speed with reduced leakage and low power consumption. The read only memory (ROM) includes multiple bit lines, multiple word lines, multiple column select lines and these lines are operatively coupled with mul... | 06/01/2010 |
| 7646622 | Memory based computation systems and methods of using the same A high performance memory based computation system comprises an array of memory cells. Each memory cell stores a logic data corresponding to a chosen combination of inputs based on a specific logic function. For improved performance, the memory cell array can be div... | 01/12/2010 |
| 7633787 | ROM memory component featuring reduced leakage current, and method for writing the same The invention relates to a ROM memory cell comprising a first terminal connected to a word line, comprising a second terminal and comprising a third terminal, the second terminal being connected to a bit line and/or the third terminal being connected to a supply lin... | 12/15/2009 |
| 7630225 | Apparatus combining once-writeable and rewriteable information storage to support data processing An information storage arrangement that combines rewriteable storage with one-time programmable (OTP) storage is managed in a manner that makes judicious use of the OTP storage. It is therefore possible to exploit the economic advantage associated with OTP storage, ... | 12/08/2009 |
| 7623367 | Read-only memory device and related method of design A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each add... | 11/24/2009 |
| 7577011 | Optimization of ROM structure by splitting A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, an... | 08/18/2009 |
| 7570505 | Memory based computation systems and methods for high performance and/or fast operations A high performance logic circuit optimizes a digital logic function by dividing the function into smaller blocks. Thus, the logic circuit is divided into smaller blocks. The smaller blocks are implemented with read-only memory (ROM), in which outputs corresponding t... | 08/04/2009 |
| 7554831 | Integrated circuit device with a ROM matrix A read only memory matrix in an integrated circuit contains data transistors coupled to both the bit lines and the word lines in data dependent ones of the cells of the matrix. A differential sense amplifier has a first input coupled to a bit line, a second input co... | 06/30/2009 |
| 7532496 | System and method for providing a low voltage low power EPROM based on gate oxide breakdown A system and method are disclosed for providing an electrically programmable read only memory (EPROM) in which each memory cell comprises an NMOS select transistor and a PMOS program transistor with a thick gate oxide and a PMOS breakdown transistor with a thin gate... | 05/12/2009 |
| 7522443 | Flat-cell read-only memory structure The integrated circuit memory comprises a memory array including a plurality of memory cells in rows and columns, the memory array being divided into a plurality of blocks of the memory cells. Each of the blocks includes a plurality of word lines arranged along the ... | 04/21/2009 |
| 7508693 | One-time-programmable (OTP) memory device and method for testing the same An OTP memory device and method for testing the same is disclosed. The memory device includes a number of memory cells and each memory cell has an initial threshold voltage. Each memory cell is programmed to have a first threshold voltage larger than a maximum value... | 03/24/2009 |
| 7505300 | Nonvolatile semiconductor memory device using nonvolatile storage elements to which data can be written only once A nonvolatile semiconductor memory device includes a nonvolatile storage element to which data is inhibited from being rewritten, a read operation control circuit which captures a read operation instruction signal in synchronization with an external input clock, and... | 03/17/2009 |
| 7480166 | Memory cell structure of metal programmable read only memory having bit cells with a shared transistor cell A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a fi... | 01/20/2009 |
| 7466578 | Methods and systems for read-only memory One embodiment of the present invention relates to a read only memory (ROM) that includes a memory cell pair. The memory cell pair includes a first memory cell and a second memory cell that share a common drain that is associated with the memory cell pair. The memor... | 12/16/2008 |
| 7457143 | Memory device with shared reference and method A memory device has a first core memory array, a second core memory array, a third core memory array and a fourth core memory array, and a first common reference section for the first core memory array and the second core memory array, and a second common reference ... | 11/25/2008 |
| 7457144 | Memory device and method for verifying information stored in memory cells A memory device comprises a plurality of first and second non-volatile memory cells arranged as an array. Each memory cell stores information. The memory device further comprises an access unit coupled to the array. The access unit stores information in the pluralit... | 11/25/2008 |
| 7443706 | High-performance memory and related method In memory array of a memory circuit, a discharging module and an auxiliary module are disposed on each column line. While accessing an objective memory unit on a column line of the memory, the memory unit discharges the corresponding row line of the objective memory... | 10/28/2008 |
| 7443719 | Superconducting circuit for high-speed lookup table A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory arra... | 10/28/2008 |
| 7440306 | Method for programming one-time programmable memory of integrated circuit A method for programming a one-time programmable memory of an integrated circuit includes the following steps: writing an instruction set into the one-time programmable memory via a first programmable interface, running a programmable self-instruction of the instruc... | 10/21/2008 |
| 7423905 | Read-only memory using linear passive elements A read-only memory (ROM) is disclosed that uses the presence or absence of linear passive electrical elements, such as resistors or capacitors, to encode zeros and ones, permitting a large-area ROM to be fabricated, possibly on a flexible substrate. The ROM includes... | 09/09/2008 |
| 7411808 | Method for reading ROM cell A method for reading data stored in a multiple bit memory cell, the memory cell comprising a switch located within an array of switches arranged in columns and rows, each switch having a control node and first and second switched nodes between which the flow of curr... | 08/12/2008 |
| 7411833 | Nitride trapping memory device and method for reading the same A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator o... | 08/12/2008 |
| 7388770 | One-time programable memory with additional programming time to ensure hard breakdown of the gate insulating film A nonvolatile semiconductor memory device includes a storage element which is programmed with information by breaking an insulating film by application of electrical stress to the storage element, a control switch which controls the application of electrical stress ... | 06/17/2008 |
