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| Number | Title | Issue Date |
| 7349236 | Electromechanical memory cell with torsional movement A memory cell uses a pair of cantilevers to store a bit of information. Changing the relative position of the cantilevers determines whether they are electrically conducting or not. The on and off state of this mechanical latch is switched by using, for example, ele... | 03/25/2008 |
| 7349238 | Ferroelectric memory device An operation switch circuit receives a command specifying operational specifications from a host. An operation control circuit controls the time of voltage application to a plate line based on an output signal from the operation switch circuit, to attain volatile-mo... | 03/25/2008 |
| 7345701 | Line buffer and method of providing line data for color interpolation A line buffer and a method of providing data to a 3×3 line interpolation processor using the line buffer in an image processing system, such as a digital camera, includes a readable and writable single memory, a buffer register having a prior data area storing firs... | 03/18/2008 |
| 7336527 | Electromechanical storage device An electromechanical storage device includes an input element that facilitates the input of data, a series of data elements, and a terminating element that facilitates the reading out of data. The data elements each have at least two stable mechanical orientations, ... | 02/26/2008 |
| 7337241 | Fast-path apparatus for receiving data corresponding to a TCP connection A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packe... | 02/26/2008 |
| 7324375 | Multi-bits storage memory A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives comm... | 01/29/2008 |
| 7317780 | Shift register circuit A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down ... | 01/08/2008 |
| 7312678 | Micro-electromechanical relay The present invention provides a micro-electromechanical relay that can produce low electrical contact resistance, and is capable of mechanical latching. More specifically, the present invention combines the clamping actions of cantilever beams with a movable shuttl... | 12/25/2007 |
| 7310260 | High performance register accesses The use of a bus clock is eliminated in communication between a cpu, or mpu, and a register block. The communication between the cpu/mpu and the register block is made combinatorial, such that the cpu/mpu does not require any acknowledge or wait signal from the regi... | 12/18/2007 |
| 7284070 | TCP offload network interface device A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packe... | 10/16/2007 |
| 7259986 | Circuits and methods for providing low voltage, high performance register files Circuits and methods are provided to implement low voltage, higher performance semiconductor memory devices such as CMOS static random access memory (SRAM) or multi-port register files. For example, circuits and methods are provided for dynamically adjusting power s... | 08/21/2007 |
| 7256484 | Memory expansion and chip scale stacking system and method The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with th... | 08/14/2007 |
| 7243282 | Method and apparatus for implementing multiple remote diagnose register chains Method and apparatus for implementing a plurality of RDR chains, wherein each of the RDR chains comprises at least one RDR is described. In one embodiment, the method comprises, responsive to execution of a first instruction identifying one of the RDR chains and one... | 07/10/2007 |
| 7237036 | Fast-path apparatus for receiving data corresponding a TCP connection A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packe... | 06/26/2007 |
| 7221817 | Beam switch structures and methods A substantially straight beam in an unbuckled state is compressed to cause the beam to buckle using an adjustable compressor. The adjustable compressor applies force to one or both ends of the beam and limits compression on the beam to allow the beam to move between... | 05/22/2007 |
| 7213090 | Data transfer apparatus for serial data transfer in system LSI A data transfer apparatus comprises a plurality of selectors each having two inputs and an output, and a transfer gate gating the transfer of data, wherein one inputs of the plurality of selectors are connected to respective bits of a data bus in the order that tran... | 05/01/2007 |
| 7191241 | Fast-path apparatus for receiving data corresponding to a TCP connection A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packe... | 03/13/2007 |
| 7188190 | Packet data processing apparatus and packet relay apparatus In a packet data processing apparatus for processing a packet received from a network by a processor, a packet data access part includes a plurality of registers arranged in series and sequentially shifts the received packet through the plurality of registers toward... | 03/06/2007 |
| 7185266 | Network interface device for error detection using partial CRCS of variable length message portions A device and method are disclosed for calculating a CRC on a message or block of data that has been divided into portions, by calculating a partial CRC corresponding to each of the portions and then combining the partial CRCs. The device and method are operable for ... | 02/27/2007 |
| 7177421 | Authentication engine architecture and method Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. Authentication engines in ... | 02/13/2007 |
| 7174014 | Method and system for performing permutations with bit permutation instructions The present invention provides permutation instructions usable in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. PPERM and PPERM3R instructions are defined to perform permutations by a sequence of... | 02/06/2007 |
| 7174393 | TCP/IP offload network interface device A system for protocol processing in a computer network has a TCP/IP Offload Network Interface Device (TONID) associated with a host computer. The TONID provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating da... | 02/06/2007 |
| 7167926 | TCP/IP offload network interface device An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offload... | 01/23/2007 |
| 7167927 | TCP/IP offload device with fast-path TCP ACK generating and transmitting mechanism A network interface device has a fast-path ACK generating and transmitting mechanism. ACKs are generated using a finite state machine (FSM). The FSM retrieves a template header and fills in TCP and IP fields in the template. The FSM is not a stack, but rather fills ... | 01/23/2007 |
| 7154984 | FIFO-register and digital signal processor comprising a FIFO-register A FIFO-register (10) according to the invention comprises a sequence of register cells (10.1, . . . ,10.m), which register cells have a data section (40) and a status section (30). Data (Din) provided at an input (20) is shifted vi... | 12/26/2006 |
| 7133940 | Network interface device employing a DMA command queue A network interface device couples a host computer to a network. The network interface device includes a processor and a DMA controller. The processor causes the DMA controller to perform multiple DMA commands before the processor takes a particular software branch.... | 11/07/2006 |
| 7124205 | Network interface device that fast-path processes solicited session layer read commands A network interface device connected to a host provides hardware and processing mechanisms for accelerating data transfers between the host and a network. Some data transfers are processed using a dedicated fast-path whereby the protocol stack of the host performs n... | 10/17/2006 |
| 7120041 | Memory device with programmable parameter controller The present invention relates to a memory device having the capability of controlling a characteristic parameter including a register controller including a nonvolatile memory unit for storing data and a parameter controller for outputting a signal corresponding to ... | 10/10/2006 |
| 7106633 | Write pointer error recovery systems and methods Write pointer error recovery systems and methods are provided. A write pointer from a write pointer circuit may cause a demultiplexer circuit to direct data from a memory cell to a desired bit location in a register. A read pointer may cause a multiplexer circuit to... | 09/12/2006 |
| 7093084 | Memory implementations of shift registers A random access memory array is used as a shift register. Data is written into different locations in a first column of the memory and then gradually transferred successively to any other number of columns in the memory. Such column-to-column data transfer is the re... | 08/15/2006 |
| 7092301 | Controller and method for writing data The present invention provides a controller that can write an operation program for a control circuit to a memory and a method for writing data, while suppressing an increase in circuit area and an increase in manufacturing cost. An ATA register is connected to a ho... | 08/15/2006 |
| 7092272 | Mechanical memory A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of memory cells, with each memory cell having a beam which can be bowed in either of two directions of curv... | 08/15/2006 |
| 7089326 | Fast-path processing for receiving data on TCP connection offload devices A network interface device provides a fast-path that avoids most host TCP and IP protocol processing for most messages. The host retains a fallback slow-path processing capability. In one embodiment, generation of a response to a TCP/IP packet received onto the netw... | 08/08/2006 |
| 7076568 | Data communication apparatus for computer intelligent network interface card which transfers data between a network and a storage device according designated uniform datagram protocol socket An interface device is connected to a host by an I/O bus and provides hardware and processing mechanisms for accelerating data transfers between a network and a storage unit, while controlling the data transfers by the host. The interface device includes hardware ci... | 07/11/2006 |
| 7069418 | Method and arrangement for instruction word generation in the controlling of functional units in a processor The invention relates to a method and an arrangement for instruction word generation in the controlling of functional units in a processor, the instruction words comprising a plurality of instruction word parts. In this case, in a program sequence, under the control... | 06/27/2006 |
| 7057946 | Semiconductor integrated circuit having latching means capable of scanning Circuits have a certain function. A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored data to respective adjacent regist... | 06/06/2006 |
| 7042898 | Reducing delays associated with inserting a checksum into a network message A first partial checksum for the header portion of a TCP header is generated on an intelligent network interface card (INIC) before all the data of the data payload of the TCP message has been transferred to the INIC. A pseudopacket with the first partial checksum a... | 05/09/2006 |
| 7038965 | Pointer generator for stack The present invention discloses a pointer generator which generates pointer values for a stack (LIFO memory). The pointer generator includes a selection input terminal and a bi-direction linear feedback shift register. The selection input terminal transmits a select... | 05/02/2006 |
| 6996070 | TCP/IP offload device with reduced sequential processing A TCP Offload Engine (TOE) device includes a state machine that performs TCP/IP protocol processing operations in parallel. In a first aspect, the state machine includes a first memory, a second memory, and combinatorial logic. The first memory stores and simultaneo... | 02/07/2006 |
| 6987686 | Performance increase technique for use in a register file having dynamically boosted wordlines For increasing the performance of a register file that is constructed to include dual-Vt bitlines or single-Vt bitlines. A boost of the drive signal for one of the transistors of a bitline circuit, preferably for the high voltage threshold read... | 01/17/2006 |
