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| Number | Title | Issue Date |
| 8164938 | Semiconductor memory device A semiconductor memory device includes a first inverter and a second inverter each having an input and an output, the output of each of the first and second inverters being connected to the input of the other so that data is stored, a CMOS switch configured to conne... | 04/24/2012 |
| 8159854 | Piezo-effect transistor device and applications A piezo-effect transistor (PET) device includes a piezoelectric (PE) material disposed between first and second electrodes; and a piezoresistive (PR) material disposed between the second electrode and a third electrode, wherein the first electrode comprises a gate t... | 04/17/2012 |
| 8134853 | High read speed electronic memory with serial array transistors Providing a serial array semiconductor architecture achieving fast program, erase and read times is disclosed herein. By way of example, a memory architecture can comprise a serial array of semiconductors coupled to a metal bitline of an electronic memory device at ... | 03/13/2012 |
| 8130529 | Semiconductor device A semiconductor device has a pair of gate electrodes extending adjacent to and non-parallel to each other, a source and/or drain region located between the pair of gate electrodes for forming a pair of transistors with the gate electrodes, and a contact electrode di... | 03/06/2012 |
| 8077493 | Semiconductor memory device A semiconductor memory device includes a memory cell array disposing a plurality of memory cells at each intersection of word lines and bit lines, the memory cell including one pair of cross-connected inverters including a transistor, a first dummy transistor having... | 12/13/2011 |
| 8000124 | Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in ... | 08/16/2011 |
| 7995367 | Circuit arrangement comprising a non-volatile memory cell and method The circuit arrangement comprises a symmetrically constructed comparator (3), a non-volatile memory cell (10) and a reference element (20). The comparator (3) exhibits a latching function, and is connected in a differential current path t... | 08/09/2011 |
| 7869245 | Semiconductor storage device with first and second pads arranged in proximity with first to fourth output transistors for reducing an excess region An excess region on a chip plane is eliminated to reduce a chip size. A plurality of data pads, which input/output data, are arranged near one side of an outer periphery of a substrate in parallel with the aforementioned one side, and a plurality of data pads, which... | 01/11/2011 |
| 7852655 | Semiconductor memory device Disclosed is a semiconductor memory device capable of realizing reduction in an SRAM unit cell area. Using as a standard configuration a parallel-type SRAM unit cell having each pair of load transistors, driver transistors and transfer transistors, all or a part of ... | 12/14/2010 |
| 7782647 | Semiconductor memory device A semiconductor memory device has a simple layout pattern of a sub hole region. The semiconductor memory device includes a segment input/output line, a first local input/output line and a second local input/output line corresponding to the segment input/output line,... | 08/24/2010 |
| 7751222 | Semiconductor memory device A basic cell comprises a memory cell capable of retaining data having at least a binary value, a first selecting transistor connected between a first terminal of the memory cell and the Mth bit line, and a second selecting transistor connected between the first term... | 07/06/2010 |
| 7626843 | Dynamic random access memory and method for accessing same An exemplary dynamic random access memory includes a first transistor (210), a second transistor (220) and a comparator (230). The first transistor includes a first gate electrode (211), a first source electrode (213) and a first d... | 12/01/2009 |
| 7623366 | Semiconductor device having a field effect source/drain region A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain reg... | 11/24/2009 |
| 7518898 | Semiconductor memory device with strengthened power and method of strengthening power of the same In a semiconductor memory device the power level of which is strengthened by using data input/output pads in a no connection state, and a method of strengthening the power of the semiconductor memory device at a stabilized power level, the semiconductor memory devic... | 04/14/2009 |
| 7457142 | Semiconductor memory device A basic cell comprises a memory cell capable of retaining data having at least a binary value, a first selecting transistor connected between a first terminal of the memory cell and the Mth bit line, and a second selecting transistor connected between the first term... | 11/25/2008 |
| 7440350 | Semiconductor integrated circuit device A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a com... | 10/21/2008 |
| 7436690 | Flat cell read only memory using common contacts for bit lines and virtual ground lines In a flat cell read only memory, two bit lines or two virtual ground lines share a common contact such that the contact is slightly adjustable in its location for inserting a local metal word line without increasing the layout area to improve the reading speed of th... | 10/14/2008 |
| 7428161 | Semiconductor memory device with MOS transistors each having floating gate and control gate A semiconductor memory device includes memory cell arrays, word lines, bit lines, column gates, sense amplifiers, and an error correcting circuit. The memory cell array includes first regions and a second region. The first region includes first element isolating reg... | 09/23/2008 |
| 7420832 | Array split across three-dimensional interconnected chips A semiconductor storage array has a first array portion on a first plane of circuitry and a second array portion on a second plane of circuitry. A composite bit line and/or a composite word line is divided and arranged to have a first portion on the first array port... | 09/02/2008 |
| 7417883 | I/O data interconnect reuse as repeater Some embodiments may include a memory with a first memory device and data pins, and a second memory device coupled with some of the data pins of the first memory device, allowing the first memory device to operate as a data repeater for the second memory device. An ... | 08/26/2008 |
| 7388773 | Random access memory with a plurality of symmetrical memory cells The invention proposes a Random Access Memory (1) with a plurality of symmetrical memory cells (2) which are connected in groups to complementary bit lines (blc, blt), and the complementary bit lines (blc, blt) are coupled through a cross coupled devic... | 06/17/2008 |
| 7379317 | Method of programming, reading and erasing memory-diode in a memory-diode array A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, f... | 05/27/2008 |
| 7376000 | Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required t... | 05/20/2008 |
| 7366044 | Systems and methods for data transfers between memory cells Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair ... | 04/29/2008 |
| 7359266 | Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit l... | 04/15/2008 |
| 7349273 | Access circuit and method for allowing external test voltage to be applied to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective well... | 03/25/2008 |
| 7345899 | Memory having storage locations within a common volume of phase change material A memory includes a volume of phase change material, a first transistor coupled to the volume of phase change material for accessing a first storage location within the volume of phase change material, and a second transistor coupled to the volume of phase change ma... | 03/18/2008 |
| 7336518 | Layout for equalizer and data line sense amplifier employed in a high speed memory device A memory device includes a memory cell array block including memory cells, a word line driver block adjacent the memory cell array block disposed in a direction in which word lines of the memory cells are arranged, a sense amplifier block adjacent the memory cell ar... | 02/26/2008 |
| 7336523 | Memory device using nanotube cells A memory device using a nanotube cell comprises a plurality of nanotube sub-cell arrays each having a hierarchical bit line structure including a main bit line and a sub-bit line. In the memory device, a nanotube cell array comprising a capacitor and a PNPN nanotube... | 02/26/2008 |
| 7336552 | Sense amplifier connecting/disconnecting circuit arrangement and method for operating such a circuit arrangement An apparatus and method for operating a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for connecting/disconnecting a sense amplifier to/from a bit line of a first cell fiel... | 02/26/2008 |
| 7333357 | Static random access memory device having reduced leakage current during active mode and a method of operating thereof An Static Random Access Memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column peripheral circuitry by bit lines and (2) an arra... | 02/19/2008 |
| 7319605 | Conductive structure for microelectronic devices and methods of fabricating such structures A conductive structure for gate lines and local interconnects in microelectronic devices. The conductive structure can be used in memory cells for SRAM devices or other types of products. The memory device cell can comprise a first conductive line, a second conducti... | 01/15/2008 |
| 7313033 | Random access memory including first and second voltage sources A random access memory including first memory cells, second memory cells, a first voltage source, and a second voltage source. The first voltage source is configured to control the first memory cells. The second voltage source is configured to control the second mem... | 12/25/2007 |
| 7310259 | Access circuit and method for allowing external test voltage to be applied to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective well... | 12/18/2007 |
| 7310256 | Semiconductor memory device A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing informa... | 12/18/2007 |
| 7307877 | Natural analog or multilevel transistor DRAM-cell Circuits and methods to design and to fabricate said circuits to accomplish a two-level DRAM cell or a multilevel DRAM cell using a natural transistor have been achieved. The usage of a natural transistor, having a threshold voltage of close to zero, as a pass trans... | 12/11/2007 |
| 7307871 | SRAM cell design with high resistor CMOS gate structure for soft error rate improvement A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through ... | 12/11/2007 |
| 7304905 | Throttling memory in response to an internal temperature of a memory device Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one embodiment a memory unit includes a memory device and a temperature measurement module coupled to the memory... | 12/04/2007 |
| 7301796 | Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required t... | 11/27/2007 |
| 7295476 | Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of... | 11/13/2007 |
