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...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
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| Number | Title | Issue Date |
| 5745420 | Integrated memory circuit with sequenced bitlines for stress test An integrated circuit having a memory array comprised of a plurality of memory cells arranged in rows and columns and a logic circuitry including column decoder and read/write circuitry, wherein each column includes a plurality of memory cells connected i... | 04/28/1998 |
| 5734187 | Memory cell design with vertically stacked crossovers A memory cell with vertically stacked crossovers. In prior memory cells, crossover connections within the memory cell were implemented in the same device layer. This wasted valuable design space, since the crossovers were therefore required to sit side-by... | 03/31/1998 |
| 5625234 | Semiconductor memory device with bit line and select line arrangement maintaining parasitic capacitance in equilibrium A semiconductor memory device in which sensing of the memory information stored in a memory cell can be carried out stably, and reliably by equilibrating a parasitic capacitance existing between a select line and its adjacent bit line pair. Each Y select ... | 04/29/1997 |
| 5615156 | Semiconductor memory device having plural memory mats with centrally located reserve bit or word lines A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approxi... | 03/25/1997 |
| 5602773 | Memory device column address selection lead layout A semiconductor memory device (20) includes N bitlines (31, 32, 33, 34) addressable by a partially decoded column address, wherein N is greater two. A column address selection lead (YSEL) has plural segments, each of which overlays a length of one of the ... | 02/11/1997 |
| 5550769 | Bit line structure for semiconductor memory device A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the pair... | 08/27/1996 |
| 5530953 | Apparatus for relocating spatial information for use in data exchange in a parallel processing environment The apparatus includes a plurality of groups of plural data paths which are connected in such a manner that each data path of one group intersects with one or more data paths of another or more data path groups. Each data path of each group is composed of... | 06/25/1996 |
| 5485419 | Memory device column address selection lead layout A semiconductor memory device (20) includes N bitlines (31, 32, 33, 34) addressable by a partially decoded column address, wherein N is greater two. A column address selection lead (YSEL) has plural segments, each of which overlays a length of one of the ... | 01/16/1996 |
| 5475643 | Semiconductor signal line system with crosstalk reduction An improved signal line system for lines such as bit lines for a semiconductor memory is disclosed. In the signal line system, a first pair of signal lines cross each other at at least one point. At least one portion of one of the signal lines of a second... | 12/12/1995 |
| 5457648 | Random access memory with digital signals running over the small signal region of the array A novel semiconductor memory having a plurality of storage devices arranged in and X-Y array wherein the Input and Output data lines of the array are routed over a portion of the memory array. The Input and Output data lines are routed symmetrically betwe... | 10/10/1995 |
| 5446772 | Integrated circuit bus An integrated circuit bus for the transmission of a serial data signal, to be used in integrated circuits, wherein the data is clocked only to one addressed register, and thus cross-talk is reduced. In the bus all information signals are contained in one ... | 08/29/1995 |
| 5420754 | Stacked board assembly for computing machines, including routing boards A system is described for arraying multi-device processing nodes in a 3-dimensional computing architecture and for flexibly connecting their ports. The topology of each processing node is of a fixed and constant physical geometry. The nodes may comprise a... | 05/30/1995 |
| 5416734 | Bit line structure for semiconductor memory device A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the pair... | 05/16/1995 |
| 5311477 | Integrated circuit memory device having flash clear A dual-port memory device provides bit lines having a crossover pattern to reduce stray end coupling capacitances. Such crossover occurs approximately in the middle of the memory array for the device. Data in one-half of the array is stored in an inverted... | 05/10/1994 |
| 5287322 | Integrated circuit dual-port memory device having reduced capacitance A dual-port memory device provides for a memory array which is divided approximately in half. Between the two halves of the array, a bit line crossover scheme is provided which minimizes stray capacitance and cross-coupling capacitance between bit lines f... | 02/15/1994 |
| 5062077 | Dynamic type semiconductor memory device A dynamic-type semiconductor memory device comprises bit lines, every two bit lines forming a folded bit line pair, every two pairs forming a bit-line unit such that one of the bit lines of the first pair extends between the bit lines of the second pair, ... | 10/29/1991 |
| 5060189 | Semiconductor device with reduced crosstalk between lines A semiconductor device such as a memory device has many sets of complementary data lines disposed parallel to one another. Mutually complementary lines are crossed with respect to each other nearly at the center such that their inter-line capacitances wit... | 10/22/1991 |
| 4980860 | Cross-coupled complementary bit lines for a semiconductor memory with pull-up circuitry A criss-crossed complementary bit line and cross-coupled pull-up means is disclosed. One bit line (26) is crossed with respect to another bit line (28) of a complementary bit line pair to reduce the effect of noise interference induced therein. P-channel ... | 12/25/1990 |
| 4769790 | Matrix data transposer A matrix data transposer is disclosed which allows data stored in a matrix format to be transposed at high speed using parallel processing techniques. In one embodiment, the data are passed through a time delay means which delays each bit of a word a diff... | 09/06/1988 |
| 4710789 | Semiconductor memory device In a semiconductor memory device, memory cells of a first column each comprising an N-channel FET are connected to a first bit line, and memory cells of a second column each comprising a P-channel FET are connected to a second bit line. The first bit line... | 12/01/1987 |
| 4485451 | System for monitoring dynamic parameters of magnetic heads A device for the determination of the dynamic characteristics of a magnetic recording and reproducing head utilizes a support for the head to be analyzed and a standard head which are juxtaposed with common carrier and are controlled by a microcomputer th... | 11/27/1984 |
| 4345318 | High performance monolithic digit driver An impedance is connected by a switching circuit, to sense/inhibit windings of a core memory at the end of each memory cycle. The result is an effectively decreased time constant for the core windings which permits faster memory operation. The circuit fur... | 08/17/1982 |
| 4238838 | Core memory wiring arrangement A large, 2 wire, 2-1/2D core memory includes four, 1K (1024) by 1280, core frames with 1280 Y conductors each stringing and inductively coupling a column of 1024 cores in each of the four frames and 4K orthogonal X conductors each stringing and inductivel... | 12/09/1980 |
| 4133050 | Early noise pulse and long duration, stabilized switching pulse A large bit size core memory which maximizes usable flux includes at least one array of low drive toroidal magnetic memory cores, a sense-inhibit conductor pair passing through the array in a given direction to inductively couple all cores in the array, a... | 01/02/1979 |
| 3997880 | Apparatus and machine implementable method for the dynamic rearrangement of plural bit equal-length records An apparatus for performing efficient transposition exchange sorts among equal length records is described. The apparatus takes advantage of the flow steering property of linkable circulating storage loops to minimize the average access time by positionin... | 12/14/1976 |
| 3982233 | Core memory with improved sense-inhibit recovery time A three wire 3D core memory which utilizes the same balanced pairs of sense-inhibit conductors to conduct both high energy common mode inhibit currents and low energy differential mode core switching signals includes pairs of antiparallel Schottky diodes ... | 09/21/1976 |
