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| Number | Title | Issue Date |
| 7345938 | Semiconductor device A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively... | 03/18/2008 |
| 7345929 | Semiconductor memory device and defect remedying method thereof A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and th... | 03/18/2008 |
| 7345937 | Open digit line array architecture for a memory array A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and... | 03/18/2008 |
| 7345899 | Memory having storage locations within a common volume of phase change material A memory includes a volume of phase change material, a first transistor coupled to the volume of phase change material for accessing a first storage location within the volume of phase change material, and a second transistor coupled to the volume of phase change ma... | 03/18/2008 |
| 7345898 | Complementary nonvolatile memory device Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvola... | 03/18/2008 |
| 7345900 | Daisy chained memory system A memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is... | 03/18/2008 |
| 7345901 | Computer system having daisy chained self timed memory chips A computer system having a memory system, the memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by ... | 03/18/2008 |
| 7342826 | Semiconductor device The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality... | 03/11/2008 |
| 7342839 | Memory cell access circuit A circuit for accessing a memory cell includes a local bitline and a local sense amplifier having a plurality of transistors. The local bitline may be connect the memory cell and the sense amplifier. A first global bitline may be connected to a first one of the plur... | 03/11/2008 |
| 7342846 | Address decoding systems and methods Systems and methods provide improved address decoding techniques for memory. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an address register that receives a reset signal, a clock signal, and an address signa... | 03/11/2008 |
| 7342816 | Daisy chainable memory chip A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip res... | 03/11/2008 |
| 7342815 | DQS signaling in DDR-III memory systems without preamble A data transmission system, particularly as part of a DDR-III memory chip communication circuit, performs a data transmission operation without preamble. The data transmission system includes at least one data line with an on die termination that can be turned on an... | 03/11/2008 |
| 7339837 | Configurable embedded processor A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support differen... | 03/04/2008 |
| 7339814 | Phase change memory array having equalized resistance A memory includes memory cells, a first line coupled to the memory cells, and a second line coupled to the memory cells. A series resistance due of the first line plus the second line at each one of the memory cells is substantially equal. ... | 03/04/2008 |
| 7340581 | Method of writing data to non-volatile memory According to a first aspect of the invention, there is provided a controller connected to a non-volatile memory and including a volatile memory, wherein the controller maintains lists in volatile memory of blocks in the non-volatile memory allocated for storage of l... | 03/04/2008 |
| 7340632 | Domain crossing device A domain crossing device for use in a semiconductor memory device, including: a unit for comparing a phase of an internal clock signal with a phase of a delay locked loop (DLL) clock signal to generate a first clock selection signal and a phase detection period sign... | 03/04/2008 |
| 7339811 | Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packi... | 03/04/2008 |
| 7339822 | Current-limited latch A current-limited latch circuit is used within a nonvolatile memory integrated circuit for decoding, programming, erase, and other operations. In one implementation, there are a number of latches connected together in parallel between two power supply lines. A curre... | 03/04/2008 |
| 7339812 | Stacked 1T-memory cell structure This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the h... | 03/04/2008 |
| 7339850 | Semiconductor memory device allowing high-speed data reading Each of a plurality of memory blocks arranged for 1 bit data is divided into two subarrays. A separate local data line is provided for each subarray and coupled to a sense amplifier via an isolation gate. A memory cell is selected in a selected subarray of a selecte... | 03/04/2008 |
| 7336541 | NAND flash memory cell programming A flash memory device, such as a NAND flash, is included having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memo... | 02/26/2008 |
| 7336519 | Stacked integrated circuit device/data processor device having a flash memory formed on top of a buffer memory A data processor includes an authentication function for judging access right. The data processor further includes a nonvolatile memory cell array formed on an insulator film or a chip, and a conductor layer provided between a logic circuit for the authentication an... | 02/26/2008 |
| 7336533 | Electronic device and method for operating a memory circuit An electronic device includes a memory cell that utilizes a bi-directional low impedance, low voltage drop full pass gate to connect a bit cell to a bit write line during a write phase, and during a read phase the full pass gate can remain off and a high input imped... | 02/26/2008 |
| 7336544 | Semiconductor device In a semiconductor device particularly including a phase change material, the reliability of the read-out operation is improved. In a read-out operation of a phase change memory, a bit line to be read out is precharged in advance with a sufficiently low voltage that... | 02/26/2008 |
| 7336552 | Sense amplifier connecting/disconnecting circuit arrangement and method for operating such a circuit arrangement An apparatus and method for operating a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for connecting/disconnecting a sense amplifier to/from a bit line of a first cell fiel... | 02/26/2008 |
| 7336535 | Semiconductor integrated circuit device A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or ... | 02/26/2008 |
| 7334326 | Method for making an integrated circuit substrate having embedded passive components A method for making an integrated circuit substrate having embedded passive components provides a reduced cost and compact package for a die and one or more passive components. An insulating layer of the substrate is embossed or laser-ablated to generate apertures f... | 02/26/2008 |
| 7336518 | Layout for equalizer and data line sense amplifier employed in a high speed memory device A memory device includes a memory cell array block including memory cells, a word line driver block adjacent the memory cell array block disposed in a direction in which word lines of the memory cells are arranged, a sense amplifier block adjacent the memory cell ar... | 02/26/2008 |
| 7336098 | High speed memory modules utilizing on-pin capacitors Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or SDRAM device connected to the memory bus via at least one transmission signa... | 02/26/2008 |
| 7333387 | Device and method for selecting 1-row and 2-row activation I claim a device and method for selecting 1-row and 2-row activation. A device includes a memory block array including a plurality of memory blocks arranged in a row-column format, a plurality of local inter-connectors to selectively couple upper local lines to lowe... | 02/19/2008 |
| 7333361 | Biosensor and sensing cell array using the same A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array inc... | 02/19/2008 |
| 7333370 | Method to prevent bit line capacitive coupling Structures, systems and methods for memory cells utilizing trench bit lines formed within a buried layer are provided. A memory cell is formed in a triple well structure that includes a substrate, the buried layer, and an epitaxial layer. The substrate, buried layer... | 02/19/2008 |
| 7333384 | Techniques for storing accurate operating current values Methods of configuring a system. More specifically, operating current values corresponding to respective memory devices of memory module may be stored in programmable elements, such as antifuses, located on the memory device, during fabrication. The operating curren... | 02/19/2008 |
| 7332815 | Semiconductor device The present invention has an object to provide a semiconductor device, an ID tag, in which delay of signal transmission with conductive layers is controlled. In addition, the other object is that a design method of such a semiconductor device is provided. A s... | 02/19/2008 |
| 7330382 | Programmable DQS preamble A method and apparatus for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted specifically for enabling the data strobe preamble. At least one of the bi... | 02/12/2008 |
| 7330992 | System and method for read synchronization of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 02/12/2008 |
| 7330367 | Stacked 1T-MTJ MRAM structure This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher ... | 02/12/2008 |
| 7330368 | Three-dimensional semiconductor device provided with interchip interconnection selection means for electrically isolating interconnections other than selected interchip interconnections In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signa... | 02/12/2008 |
| 7331010 | System, method and storage medium for providing fault detection and correction in a memory subsystem A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the... | 02/12/2008 |
| 7330381 | Method and apparatus for a continuous read command in an extended memory array The present invention relates to a memory on a silicon microchip, comprising a serial input/output and an integrated memory array addressable under N bits. According to the present invention, the memory comprises means for storing a most significant address allocate... | 02/12/2008 |
