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| Number | Title | Issue Date |
| 4755902 | Electronic apparatus with detachable member arranged to detect erroneous mounting of the detachable member An electronic apparatus adapted to be used with a detachable member, such as a memory pack. The apparatus includes a pair of terminals arranged in the electronic apparatus for detecting an incorrect connection of the electronic apparatus with the memory p... | 07/05/1988 |
| 4754401 | System for servicing a removable RAM package for an ambulatory medical monitor An apparatus for servicing a removable RAM package of an ambulatory medical monitor is disclosed. The RAM package comprises a RAM for storing blood pressure data and operating parameters and a real time timer. Both are coupled to a multipin edge connector... | 06/28/1988 |
| 4729119 | Apparatus and methods for processing data through a random access memory system Apparatus and methods are disclosed for providing an increased flexibility and rate in processing data in a random access memory (RAM) system. The apparatus comprises, in a first embodiment, a switching circuit which is coupled to the word lines of the RA... | 03/01/1988 |
| 4694428 | Semiconductor memory In a semiconductor memory, a memory cell array is divided into a plurality of sub arrays in a direction perpendicular to word lines. In each sub array sub word lines and bit lines are disposed to intersect each other and memory cells are disposed at all t... | 09/15/1987 |
| 4692900 | Semiconductor memory device having block pairs A semiconductor memory device provided with at least one block pair. Each block contains therein bit line pairs, word lines, memory cells, and circuitry for writing data by cooperating with the bit line pairs. The wiring pattern of the writing part locate... | 09/08/1987 |
| 4660998 | Dot-matrix printer with font cartridge unit A dot-matrix printer of the invention uses a font cartridge unit storing in advance character pattern data corresponding to characters other than standard characters. The font cartridge unit comprises a ROM or RAM storing character pattern data in a stora... | 04/28/1987 |
| 4660999 | Dot-matrix printer with font cartridge unit A dot-matrix printer of the invention uses a font cartridge unit storing in advance character pattern data corresponding to characters other than standard characters. The font cartridge unit has a memory area divided into a plurality of page areas, and co... | 04/28/1987 |
| 4660174 | Semiconductor memory device having divided regular circuits In a semiconductor memory device including word lines (WL) and bit lines (BL), a regular pattern circuit area comprising elements regularly arranged in line with the word lines and/or the bit lines is divided into a plurality of blocks (1-1, 1-2). Provide... | 04/21/1987 |
| 4627028 | Memory decoder circuit In an NOR decoder for a static random access memory the individual transistor gates (30) are coupled to metallization tracks (31) via polysilicon contact islands (33). The gates of selected transistors are divided into two portions (20a, 20b) disposed on ... | 12/02/1986 |
| 4593376 | System for vending program cartridges which have circuitry for inhibiting program usage after preset time interval expires A vending machine stores a plurality of video game programs which may be selected for purchase. The game program is transferred to a programmable cartridge which the user inserts into the machine. The programmable cartridge is then removed for use on a se... | 06/03/1986 |
| 4592018 | Removable RAM package for ambulatory medical monitor A removable package for use primarily in an ambulatory monitoring device, such as a medical monitor includes a RAM and a power supply. The RAM package is connected to an external device via an edge connector which includes interlock means for sensing when... | 05/27/1986 |
| 4586169 | Semiconductor memory circuit and large scale integrated circuit using the same A large scale integrated circuit including therein a logical gate circuit and a memory circuit is disclosed in which a large number of circuit blocks each having the same structure and including at least eight transistors and at least five resistors are a... | 04/29/1986 |
| 4586171 | Semiconductor memory A random access type semiconductor memory comprises a plurality of word lines (44; 54) of a metal arranged in parallel, at least first to fourth bit lines (BL1, BL2, BL1, BL2) orthogonal to the word lines, a plurality of memory cells (48; 58a, 58b), each ... | 04/29/1986 |
| 4570241 | FET Storage with partitioned bit lines A circuit arrangement is described with a sense latch for increasing the number of dynamic FET storage cells on bit lines (BL) connected to this sense latch (SL). The storage cells proper are arranged in a semiconductor structure having a diffusion layer ... | 02/11/1986 |
| 4566082 | Memory pack addressing system Disclosed herein is a system for addressing a memory pack having a plurality of memory chips such as RAMs or ROMs. Each memory chip receives address signals and a chip enable signal. A chip selector generates the chip enable signal in response to a feedba... | 01/21/1986 |
| 4558339 | Electrically alterable, nonvolatile floating gate memory device A novel, nonvolatile, floating gate memory structure, and a method for its fabrication, is described wherein the floating gate is substantially shielded from the substrate by the program or control gate. The program or control gate is provided with an ape... | 12/10/1985 |
| 4535423 | Semiconductor memory device A semiconductor memory device which includes a plurality of memory cells each having a capacitor, and peripheral circuits of the memory cells, integrated on a semiconductor substrate. Each capacitor has a storage electrode and an electrode opposite to the... | 08/13/1985 |
| 4535424 | Solid state three dimensional semiconductor memory array A memory circuit including several semiconductor substrates, each containing addressable memory elements, address receiving circuitry for receiving address signals and for providing data from the memory in response to the address signals, control circuitr... | 08/13/1985 |
| 4525809 | Integrated circuit A semiconductor integrated circuit having improved information processing function is disclosed. The integrated circuit comprises a semiconductor substrate, an information processing circuit fabricated on the substrate, a plurality of unit cells each havi... | 06/25/1985 |
| 4506347 | Placement of clock circuits for semiconductor memory A dynamic random access memory (10) is fabricated on a substrate (12) and is divided into memory sections (14, 16). Memory cells (46) are connected to bit lines (18-28, a and b), which are organized into pairs that are connected to respective sense amplif... | 03/19/1985 |
| 4490813 | Frequency determining apparatus for a synthesized radio Apparatus is provided for containing information designating the frequency of operation of a synthesized radio frequency receiver. The apparatus is programmable and selectively addressable with respect to operating frequency.... | 12/25/1984 |
| 4490697 | Signal propagating device for a plurality of memory cells There is provided a signal propagating device for receiving an input signal at an input end thereof and supplying the input signal to a plurality of memory cells arranged in one row. The signal propagating device includes a word line connected to transmit... | 12/25/1984 |
| 4485459 | Redundant columns for byte wide memories Apparatus is provided for substituting a spare column of memory cells in a byte wide memory for a defective column of cells in such memory. The apparatus includes a spare column of memory cells, an electrically conductive line 13, a spare decoder 16 for s... | 11/27/1984 |
| 4459687 | Integrated circuit having a multi-layer interconnection structure An integrated circuit having a multi-layer interconnection structure comprises a logic section of series-connected MOS FETs each having a gate input connection layer made of a polysilicon layer on a semiconductor substrate of one conductivity type and sou... | 07/10/1984 |
| 4456977 | Semiconductor memory device A semiconductor memory device having a large memory capacity and an improved read-out function is disclosed. The device comprises a plurality of word lines extended in the row direction, a plurality of pairs of data lines extended in the column direction ... | 06/26/1984 |
| 4446475 | Means and method for disabling access to a memory An integrated circuit chip having a digital memory is provided wherein direct access to at least a portion of the memory is prevented. Contact pads having coupling lines to couple the contact pads to the memory bus are provided. A security code can be pro... | 05/01/1984 |
| 4418399 | Semiconductor memory system A semiconductor memory system providing memory matrix area where many word lines and bit lines cross in the row and column directions. Memory cells are arranged at the intersections resulting in high integration density. A plurality of peripheral circuit ... | 11/29/1983 |
| 4400794 | Memory mapping unit A memory mapping unit enables different sized memory boards to be mapped in any order into any size memory address boundary in a microprocessor. Any 2K sized memory board (where NࣘKࣘM) can be mapped to any 2N address boundary. To... | 08/23/1983 |
| 4398235 | Vertical integrated circuit package integration A compact assembly of similar type integrated circuit packages having a functionally similar terminal lead in non-corresponding lead positions. Two interconnection packages, of a type similar to the integrated circuit packages, are nested between the inte... | 08/09/1983 |
| 4375665 | Eight bit standard connector bus for sixteen bit microcomputer using mirrored memory boards A microcomputer system uses a standardized S-100 bus with eight bit Data In and eight bit Data Out lines, but has a sixteen bit microprocessor with sixteen bit bidirectional data input/output terminals. An arrangement of mirror image pairs of memory board... | 03/01/1983 |
| 4371928 | Interface for controlling information transfers between main data processing systems units and a central subsystem In a data processing system, a system memory includes first memory modules having a data path of a first bit width and second memory modules having a data path of a second bit width with the first bit width being less than the second bit width. A central ... | 02/01/1983 |
| 4368523 | Liquid crystal display device having redundant pairs of address buses Disclosed is a memory device having a plurality of memory cells arranged in a matrix form; address buses connected to the memory cells and forming respective rows of the matrix; and data buses connected to the memory cells and forming respective columns o... | 01/11/1983 |
| 4367540 | Dynamic memory with an interchangeable pair of data lines and sense amplifiers Four adjacent data lines are divided into two pairs. A first pair of the data lines is connected to one differential sense amplifier and a second pair of the data lines is connected to another differential sense amplifier, and vice versa, depending upon f... | 01/04/1983 |
| 4347446 | Emitter coupled logic circuit with active pull-down An emitter coupled logic gate incorporating an active pull-down transistor in the pull-down circuit with bias connections for the pull-down transistor including components in the differential input circuit of the gate so that the pull-down transistor is a... | 08/31/1982 |
| 4330825 | Device for automatic control of the storage capacity put to work in data processing systems A device is provided for automatically determining the storage capacity of a data processing or transmission system and signalling when the storage capacity is inadequate to handle an incoming address. The store includes a plurality of storage fractions m... | 05/18/1982 |
| 4327355 | Digital device with interconnect matrix Disclosed is a digital device on a semiconductor chip, which is comprised of a plurality of storage means for storing digital signals therein, a plurality of functional means for performing functional operations on the digital signals, and an interconnect... | 04/27/1982 |
| 4281397 | Virtual ground MOS EPROM or ROM matrix An array of rows and columns of memory cells of the virtual ground type employs a cell layout which has one column line per column instead of requiring extra lines for ground. Half of the column lines are used as outputs and half as ground. One output lin... | 07/28/1981 |
| 4214302 | Eight bit standard connector bus for sixteen bit microcomputer A microcomputer system uses a standardized S-100 bus with eight bit Data In and eight bit Data Out lines, but has a sixteen bit microprocessor with sixteen bit bidirectional data input/output terminals. An arrangement is provided to cross-connect the Data... | 07/22/1980 |
| 4213177 | Eight bit standard connector bus for sixteen bit microcomputer using mirrored memory boards A microcomputer system uses a standardized S-100 bus with eight bit Data In and eight bit Data Out lines, but has a sixteen bit microprocessor with sixteen bit bidirectional data input/output terminals. An arrangement of mirror image pairs of memory board... | 07/15/1980 |
| 4199818 | Electrical connection matrix plane An electrical woven electrical connection matrix plane intended primarily for switching electric signals in electronic circuits, which is made from interwoven insulation threads and X and Y current conductors, the X and Y current conductors at intersectio... | 04/22/1980 |
