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| Number | Title | Issue Date |
| 7379328 | Semiconductor device Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory... | 05/27/2008 |
| 7379334 | Memory card, semiconductor device, and method of controlling memory card A semiconductor device includes a transfer section which receives, from an external source, a second program for modifying a function of a first program stored in a read-only memory (ROM) and information required in activation of the second program, and which writes... | 05/27/2008 |
| 7379316 | Methods and apparatus of stacking DRAMs Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards. ... | 05/27/2008 |
| 7376000 | Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required t... | 05/20/2008 |
| 7375971 | Memory module with an electronic printed circuit board and a plurality of semiconductor chips of the same type In a first embodiment, the invention provides a memory module having an electronic printed circuit board and a plurality of semiconductor chips of the same type that are mounted on at least one outer face of the printed circuit board. The printed circuit board has a... | 05/20/2008 |
| 7376002 | Semiconductor memory device In a multiport SRAM memory cell of the present invention, an access transistor of a first port is disposed in a p-type well, and an access transistor of a second port is disposed in a p-type well. The gates of all of transistors disposed in a memory cell extend in t... | 05/20/2008 |
| 7376013 | Compact virtual ground diffusion programmable ROM array architecture, system and method A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array having M rows and N columns. A shared source line is associated with ea... | 05/20/2008 |
| 7372766 | Semiconductor memory device A semiconductor memory device may include a switching unit to selectively connect a bitline pair and a pair of input/output lines in response to a column selection line signal; a column selection line voltage generator to generate a column selection line voltage; an... | 05/13/2008 |
| 7372715 | Architecture and method for NAND flash memory A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitl... | 05/13/2008 |
| 7372744 | Memory system which copies successive pages, and data copy method therefor A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit... | 05/13/2008 |
| 7372753 | Two-cycle sensing in a two-terminal memory array having leakage current A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected tra... | 05/13/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7370141 | Memory system A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller ... | 05/06/2008 |
| 7369445 | Methods of operating memory systems including memory devices set to different operating modes and related systems A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device o... | 05/06/2008 |
| 7370166 | Secure portable storage device In one embodiment of the present invention, a secure storage system includes a removable storage device having a secure storage area for storage of secure data and a public storage area and device port for coupling the removable storage device to a host, the removab... | 05/06/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7366051 | Word line driver circuitry and methods for using the same Word line driver circuitry for selectively charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology, where a first transistor is driven by a signal, DOUT, and a second transistor is driven by a time-delayed co... | 04/29/2008 |
| 7365006 | Semiconductor package and substrate having multi-level vias fabrication method A semiconductor package and substrate having multi-level plated vias provide a high density blind via solution at low incremental cost. Via are half-plated atop a circuit pattern and then a second via half is added to complete the via after isolation of elements of ... | 04/29/2008 |
| 7365355 | Programmable matrix array with phase-change material A phase-change material is proposed for coupling interconnect lines an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer between the phase change material and at least one of the lines. The matrix ... | 04/29/2008 |
| 7366015 | Semiconductor integrated circuit device, production and operation method thereof A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells fun... | 04/29/2008 |
| 7366821 | High-speed memory system A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein the plurality of memories are controlled by the switch. By suppressing ... | 04/29/2008 |
| 7366864 | Memory hub architecture having programmable lane widths A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled t... | 04/29/2008 |
| 7364464 | Electrical docking connector An electrical connector for engaging with a mating connector comprising an insulative housing, a plurality of contacts in the housing and a metallic shell covering the insulative housing. The metallic shell comprises a frame with at least one tab arranged at the fro... | 04/29/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7363422 | Configurable width buffered module A memory system architecture/interconnect topology includes a configurable width buffered module having a configurable width buffer device. The configurable width buffer device is coupled to at least one memory device on the configurable width memory module. The con... | 04/22/2008 |
| 7362638 | Semiconductor memory device for sensing voltages of bit lines in high speed The present invention relates to a semiconductor memory device for sensing voltages of bit lines in high speed. The semiconductor memory device for sensing voltages of bit lines in high speed includes: a first bit line pair to a fourth bit line pair each coupled to ... | 04/22/2008 |
| 7362640 | Apparatus and method for self-refreshing dynamic random access memory cells A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the mai... | 04/22/2008 |
| 7361550 | Methods of fabricating semiconductor memory devices including electrode contact structures having reduced contact resistance A semiconductor memory device includes a semiconductor substrate having an active region therein, an insulating layer on the substrate, and a lower electrode conductive pad extending through the insulating layer. The lower electrode conductive pad electrically conta... | 04/22/2008 |
| 7362649 | Memory control device and memory control method There is provided memory control device and memory control method, which can prevent wiring complication by many crossing wirings, and reduction of yield and quality. When a memory control device CC1 selects a memory chip CC2, an internal circuit of a ... | 04/22/2008 |
| 7362641 | Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memo... | 04/22/2008 |
| 7359227 | Shared address lines for crosspoint memory A crosspoint memory includes a shared address line. The shared address line may be coupled to cells above and below the address line in one embodiment. Voltage biasing may be utilized to select one cell, and to deselect another cell. In this way, each cell may be ma... | 04/15/2008 |
| 7359252 | Memory data bus structure and method of transferring information with plural memory banks A data bus structure for a dynamic random access memory (DRAM) according to the present invention includes a series of data buses, each shared by a plurality of memory banks, and a switching device to selectively couple the data buses to a global data bus to enable ... | 04/15/2008 |
| 7359204 | Multiple cover memory card A memory card including a module comprising at least a printed circuit board having an electronic circuit device mounted thereto and at least one I/O pad and at least one test pad disposed thereon. The module is inserted into a complementary cavity formed within a c... | 04/15/2008 |
| 7359228 | Semiconductor memory device capable of realizing a chip with high operation reliability and high yield A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is construc... | 04/15/2008 |
| 7358548 | Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner Buffers are arranged in a concentrated manner in a region distant from pads. The region refers to a region in a main region of a semiconductor integrated circuit, except for a central processing unit, a non-volatile memory and a volatile memory. As the buffer requir... | 04/15/2008 |
| 7358758 | Apparatus and method for enabling a multi-processor environment on a bus The present invention provides a technique for enabling multiple devices to be interfaced together over a bus that requires dynamic impedance controls. In one embodiment, an apparatus is provided for enabling a multi-device environment on a bus, where the bus requir... | 04/15/2008 |
| 7359229 | Semiconductor memory device and method of operating same There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this ... | 04/15/2008 |
| 7359226 | Transistor, memory cell array and method for forming and operating a memory device A substrate forming an array of vertical transistor cells for selecting one of a plurality of memory cells and wherein each memory cell couples a transistor to a bit line via a memory element and is addressable by selecting two word lines and a bit line is disclosed... | 04/15/2008 |
| 7359273 | Semiconductor memory device having layout for minimizing area of sense amplifier region and word line driver region A semiconductor memory device has a layout that minimizes the area required for sense amplifier and word line driver regions. In the semiconductor memory device of the present invention, decoding drivers are arranged in sense amplifier regions. Further, the wiring f... | 04/15/2008 |
| 7359241 | In-service reconfigurable DRAM and flash memory device A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical p... | 04/15/2008 |
