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| Number | Title | Issue Date |
| 7307862 | Circuit and system for accessing memory modules A circuit and system for improving signal integrity in a memory system. The circuit has a transmission line having a dampening impedance between a driver and a branch point of the transmission line. The circuit also has a termination impedance having one end coupled... | 12/11/2007 |
| 7302982 | Label applicator and system A label applicator including a support surface having a central area and curving downwardly from the central area. A post assembly extends up from the central area such that a label having a label through-hole can be positioned in a support position generally on the... | 12/04/2007 |
| 7303820 | Heat spreader for display device A heat spreader for a display device, such as a plasma display panel, a light emitting diode or a liquid crystal display, which includes at least one sheet of compressed particles of exfoliated graphite having two major surfaces, both of which have a layer of an adh... | 12/04/2007 |
| 7304352 | Alignment insensitive D-cache cell A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one rea... | 12/04/2007 |
| 7304877 | Semiconductor memory device with uniform data access time A semiconductor memory device includes: a core region having a plurality of bank sets for outputting/storing a data in response to an inputted address, wherein each bank set includes one bank, one row address control unit and two column address control units; and a ... | 12/04/2007 |
| 7304905 | Throttling memory in response to an internal temperature of a memory device Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one embodiment a memory unit includes a memory device and a temperature measurement module coupled to the memory... | 12/04/2007 |
| 7305574 | System, method and storage medium for bus calibration in a memory subsystem A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memor... | 12/04/2007 |
| 7305594 | Integrated circuit in a maximum input/output configuration A memory includes input/output paths and electrical leads. Each of the input/output paths are coupled to separate electrical leads. The memory is configured to operate in a test architecture and an operating architecture. In the test architecture, logic enables a gr... | 12/04/2007 |
| 7301796 | Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required t... | 11/27/2007 |
| 7301847 | Method and device for a main board commonly associated with DDR2 or DDR1 A method and device for a main board commonly shared with DDR2 or DDR1 includes allowing the main board being associated with a voltage transducer and a DDR2 connector, the voltage transducer outputting a voltage suitable for DDR2 to the DDR2 connector via the outpu... | 11/27/2007 |
| 7301794 | Non-volatile memory array with simultaneous write and erase feature A non-volatile transistor memory array has individual cells with a current injector and a non-volatile memory transistor. Injector current gives rise to charged particles that can be stored in the memory transistor by tunneling. When a row of the array is activated ... | 11/27/2007 |
| 7301793 | Semiconductor memory device A semiconductor memory device comprises a plurality of memory cell groups. Each memory cell group includes at least two memory cells. Each memory cell group includes a read section and a write section. The data of a memory cell is read from one bit line to a read gl... | 11/27/2007 |
| 7301802 | Circuit arrays having cells with combinations of transistors and nanotube switching elements Circuit arrays having cells with combinations of transistors and nanotube switches. Under one embodiment, a circuit array includes a plurality of cells arranged in an organization of words, each word having a plurality of bits. Each cell is responsive to a bit line,... | 11/27/2007 |
| 7301811 | Cost efficient nonvolatile SRAM cell A cost efficient nonvolatile memory cell may include an inverter, an access gate coupled to the inverter for controlling access to the memory cell, and a control gate. The inverter may include a floating gate at an input of the inverter, the floating gate formed in ... | 11/27/2007 |
| 7301836 | Feature control circuitry for testing integrated circuits An integrated circuit is provided that includes testing circuitry for testing input-output circuits. The integrated circuit contains input-output circuits that each have associated input-output pins and input and output buffers. Each input-output circuit has associa... | 11/27/2007 |
| 7301831 | Memory systems with variable delays for write data signals Systems and methods for generating write data signals having variable delays for use in write operations to memory components are provided. These memory systems and methods include receiving a write data signal and a corresponding data valid or timing signal (also r... | 11/27/2007 |
| 7301819 | ROM with a partitioned source line architecture A partitioned source line architecture for reducing leakage and power in a ROM. In one embodiment, a ROM is comprised of a plurality of storage cells organized as an array having M rows and N columns. Each column is associated with a precharged source line that is p... | 11/27/2007 |
| 7298665 | Dual-mode decoder circuit, integrated circuit memory array incorporating same, and related methods of operation In an embodiment of the invention an integrated circuit includes a memory array having a first plurality of decoded lines traversing across the memory array and a pair of dual-mode decoders, each decoder coupled to each of the plurality of decoded lines a respective... | 11/20/2007 |
| 7298662 | Semiconductor device with power down arrangement for reduce power consumption A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both ... | 11/20/2007 |
| 7298638 | Operating an electronic device having a vertical gain cell that includes vertical MOS transistors A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a source region, and a second vertical MOS transistor merged with the se... | 11/20/2007 |
| 7295486 | Memory and driving method therefor A memory and a driving method therefor is provided. A j-th bank select MOS transistor is coupled to a j-th bit line and controlled by a bank select line. A j-th BD region is coupled to the j-th bank select MOS transistor. Gate(i, j) of memory cell M (i, j) is couple... | 11/13/2007 |
| 7295487 | Storage circuit and method therefor Storage circuits (180-183 and 280-281) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit 100), shared complementary write bit lines (101, 102), separate read bit lines (1... | 11/13/2007 |
| 7296129 | System, method and storage medium for providing a serialized memory interface with a bus repeater A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies v... | 11/13/2007 |
| 7295459 | Static random access memory (SRAM) cell An SRAM memory cell employing thin-film transistors is provided having a first transmission gate, a second transmission gate and a bi-stable flip-flop comprising a first and a second inverter disposed between the first and the second transmission gate. A third trans... | 11/13/2007 |
| 7295484 | Temperature based DRAM refresh A system for controlling the refresh cycles of a DRAM cell array based upon a temperature measurement. During active mode, a refresh request indication based on a measured temperature is provided to a DRAM controller (e.g. of another integrated circuit die), wherein... | 11/13/2007 |
| 7295454 | Semiconductor memory device and arrangement method thereof A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word li... | 11/13/2007 |
| 7295485 | Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations The present invention provides a solution for long master bit lines in a large capacity memory device. A master bit line is partitioned by at least one switching transistor placed on the master bit line. ... | 11/13/2007 |
| 7295465 | Thin film magnetic memory device reducing a charging time of a data line in a data read operation During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is comp... | 11/13/2007 |
| 7292486 | Methods and circuits for latency control in accessing memory devices Methods of providing a delay for access to a memory device can include adjusting a delay for access to data during memory operations based on at least one parameter associated with a reduction in voltage levels provided to the memory. Related circuits are also discl... | 11/06/2007 |
| 7291923 | Tapered signal lines In an integrated circuit, a layer including a plurality of conductive wires is described. A first wire, having sidewalls, is tapered from a proximal end which has a first width to a distal end which has a second width, to reduce width from the first width to the sec... | 11/06/2007 |
| 7290331 | Component mounting apparatus and component mounting method In a component mounting apparatus in which integrated components having a chip-on-chip structure are formed by mounting upper chips on lower chips. The lower chips picked up from a component carrying-in unit by a component carrying-in head are placed on a mounting s... | 11/06/2007 |
| 7292497 | Multi-bank memory A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another bank. Banks in different rows can be simultaneously accessed. ... | 11/06/2007 |
| 7292454 | System and method for optimizing printed circuit boards to minimize effects of non-uniform dielectric A system and method for minimizing the effects of non-uniform dielectric properties includes forming traces on printed circuit boards (PCB) where the fibers within the printed circuit boards are non-rectangular with respect to the rectangular edges of the circuit bo... | 11/06/2007 |
| 7292465 | Ferroelectric random access memory device, display drive integrated circuit, and electronic apparatus A ferroelectric random access memory device, includes at least one bit line extending in a first direction; a plurality of first active regions, arranged in the first direction a predetermined distance from each other on one side of the bit line, each being connecte... | 11/06/2007 |
| 7292482 | Multivibrator protected against current or voltage spikes A multivibrator circuit includes a first data transfer port that receives, as input, multivibrator input data, a first, master, latch cell connected on the output side of the first transfer port, a second, slave, latch cell, and a second data transfer port placed be... | 11/06/2007 |
| 7292493 | Semiconductor device with electrically broken fuse and its manufacture method An electric fuse is formed over a semiconductor substrate, the electric fuse being broken when a current flows therethrough. A breaker transistor is formed in a first surface layer of the semiconductor substrate of a first conductivity type, the breaker transistor i... | 11/06/2007 |
| 7290078 | Serial memory comprising means for protecting an extended memory array during a write operation The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. T... | 10/30/2007 |
| 7289386 | Memory module decoder A memory module connectable to a computer system includes a printed circuit board, a plurality of memory devices coupled to the printed circuit board, and a logic element coupled to the printed circuit board. The plurality of memory devices has a first number of mem... | 10/30/2007 |
| 7289346 | Semiconductor integrated circuit In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplificati... | 10/30/2007 |
| 7289347 | System and method for optically interconnecting memory devices A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable t... | 10/30/2007 |
