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| Number | Title | Issue Date |
| 8189359 | Nonvolatile memory device having different types of metal lines Provided is a nonvolatile memory device, including a memory cell array region, a decoder and an interface region. The memory cell array region includes multiple word lines. The decoder supplies multiple voltages to the word lines through multiple first type metal li... | 05/29/2012 |
| 8189360 | Semiconductor memory device A semiconductor memory device includes first and second element regions having a rectangular bent portion and a pair of straight line portions connected to both ends of the bent portions, respectively. The pair of straight line portions extends in an opposite direct... | 05/29/2012 |
| 8184463 | Semiconductor apparatus The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—... | 05/22/2012 |
| 8184464 | Flash memory A flash memory includes a controller unit and dies. The dies are connected to a controller unit. Each of the dies includes an upper face and a lower face. Each of the dies includes at least one power supply pad, at least one grounding pad, at least one input/output ... | 05/22/2012 |
| 8174859 | Memory device interface methods, apparatus, and systems Apparatus and systems may include a substrate and a first memory device coupled to the substrate using a through wafer interconnect (TWI). An example may include an interface chip having a via to accommodate connection of the memory device to the substrate. Other ap... | 05/08/2012 |
| 8174860 | Semiconductor memory device having improved voltage transmission path and driving method thereof Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more se... | 05/08/2012 |
| 8164937 | Digital potentiometer using third dimensional memory A digital potentiometer using third dimensional memory includes a switch configured to electrically couple one or more resistive elements with a first pin and a second pin, and a non-volatile register configured to control the switch. In one example, the non-volatil... | 04/24/2012 |
| 8164936 | Switched memory devices A data storage system includes a plurality of memory devices for storing data. The plurality of memory devices is classified into a plurality of groups of memory devices. A control circuit is adapted to provide concurrent memory access operations to the plurality of... | 04/24/2012 |
| 8144497 | Self-identifying stacked die semiconductor components A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die st... | 03/27/2012 |
| 8144495 | Method for programming an electronic circuit and electronic circuit The invention relates to a method for producing an electronic circuit, and to an electronic circuit, having at least one organic electrical functional layer and at least one data storage unit, the data storage unit being configured with two electrically conductive l... | 03/27/2012 |
| 8144496 | Memory system with multi-level status signaling and method for operating the same A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a vo... | 03/27/2012 |
| 8139387 | Method of erasing a memory device including complementary nonvolatile memory devices Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvola... | 03/20/2012 |
| 8116113 | Cross-point semiconductor memory device and method of manufacturing the same A cross-point semiconductor memory device includes: a plurality of first wirings extending in a first direction; a plurality of second wirings positioned on a layer different from the first wirings to extend in a second direction different from the first direction; ... | 02/14/2012 |
| 8116114 | Semiconductor memory and system A pair of access control circuits having bit line pairs wired corresponds to a same data terminal and is assigned different addresses. During a test mode, a data swap circuit prohibits swapping of connections between a pair of data terminals and a pair of data lines... | 02/14/2012 |
| 8116110 | Array architecture including mirrored segments for nonvolatile memory device A memory device including nonvolatile memory cells arrayed in a first direction and in a second direction, a plurality of first lines extending in the first direction for coupling memory cells arrayed in the first direction, and a plurality of second lines extending... | 02/14/2012 |
| 8116112 | Semiconductor memory device A semiconductor memory apparatus includes: a bit line; a word line; a local bit line; a first switch unit provided between the local bit line and the bit; a memory cell connected to the bit line and the word line; a memory cell array including the memory cell; a fir... | 02/14/2012 |
| 8116111 | Nonvolatile memory devices having electromagnetically shielding source plates Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including a cell array region, memory cell transistors disposed at the cell array region, bitlines disposed on the memory cell trans... | 02/14/2012 |
| 8111536 | Semiconductor memory device The memory cell array has memory cells each positioned at respective intersections between a plurality of first wirings and a plurality of second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The res... | 02/07/2012 |
| 8111535 | Presetable RAM A programmable volatile memory cell has a reset device in communication with a bit store. The reset device may produce a high or low logic state within a latch loop when activated by an assertive logic level on a reset line. A set of mask programmable vias may be pr... | 02/07/2012 |
| 8107271 | Termination circuits and semiconductor memory devices having the same A termination circuit is connected to an input buffer receiving a data signal, and includes at least one termination resistor connected to the input buffer for impedance matching. At least one switch controls a connection between the input buffer and a corresponding... | 01/31/2012 |
| 8098508 | Configurable inputs and outputs for memory stacking system and method Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablemen... | 01/17/2012 |
| 8098509 | Nonvolatile semiconductor memory device, method of fabricating the nonvolatile semiconductor memory device and process of writing data on the nonvolatile semiconductor memory device A nonvolatile semiconductor memory device includes a semiconductor substrate, a plurality of first element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a first cell array region into a band shape, a plurality of seco... | 01/17/2012 |
| 8094478 | Nonvolatile memory device having a plurality of memory blocks A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously bet... | 01/10/2012 |
| 8089795 | Memory module with memory stack and interface with enhanced capabilities A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated ci... | 01/03/2012 |
| 8089796 | Information recording and reproducing device According to one embodiment, an information recording and reproducing device includes a first layer, a second layer and a recording layer. The recording layer is provided between the first and second layers and is capable of reversibly transitioning between a first ... | 01/03/2012 |
| 8068357 | Memory controller with multi-modal reference pad A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The re... | 11/29/2011 |
| 8064238 | System using non-volatile resistivity-sensitive memory for emulation of embedded flash memory Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity pro... | 11/22/2011 |
| 8059441 | Memory array on more than one die For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the me... | 11/15/2011 |
| 8059442 | ROM array with shared bit-lines Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with... | 11/15/2011 |
| 8050072 | Dual stage sensing for non-volatile memory A method and apparatus for accessing a non-volatile memory cell. In some embodiments, a memory block provides a plurality of memory cells arranged into rows and columns. A read circuit is configured to read a selected row of the memory block by concurrently applying... | 11/01/2011 |
| 8050073 | Semiconductor memory device A semiconductor memory device includes a memory block having first and second word lines extending in a first direction and bit lines extending in a perpendicular second direction; a first driver region at a side of the memory block in the first direction driving th... | 11/01/2011 |
| 8045356 | Memory modules having daisy chain wiring configurations and filters Examples described include memory units coupled to a controller using a daisy chain wiring configuration. A filter located between a first memory unit and the controller attenuates a particular frequency, which may improve ringback in a signal received at the memory... | 10/25/2011 |
| 8040710 | Semiconductor memory arrangement A semiconductor memory arrangement includes a circuit board having at least a first layer and a second layer, a plurality of memory units, and a first control device and a second control device adapted to receive command and address signals. A first bus system is di... | 10/18/2011 |
| 8036012 | Device for controlling the activity of modules of an array of memory modules A memory device includes an array of memory modules, a global controller, and a local controller for each memory module in the array of memory modules being configured to deliver to the global controller an activity signal reflecting an activity of the respective me... | 10/11/2011 |
| 8036011 | Memory module for improving signal integrity and computer system having the same A memory module includes a plurality of buses and a plurality of memory chips arranged close to each other along each of the plurality of buses. An N-th memory chip, where N is an integer, of the plurality of memory chips is connected to any one of the plurality of ... | 10/11/2011 |
| 8018753 | Memory module including voltage sense monitoring interface Memory devices and systems include a voltage sense line for addressing voltage tolerances across variable loadings. The memory devices and systems comprise a memory module connector with a first plurality of pins coupled to circuitry on a memory module, and a second... | 09/13/2011 |
| 8014184 | Radiation hardened memory cell A memory cell has a data value storage circuit and a data address circuit that includes a first address transistor formed in a first address transistor well and a second address transistor formed in a second address transistor well. The first address transistor is c... | 09/06/2011 |
| 8004870 | Memory chips and judgment circuits thereof A memory chip is provided. The memory chip operates at modes and includes an option pad and a judgment circuit. The judgment circuit is coupled to the option pad generates a judgment signal according to the current status of the option pad. The judgment signal indic... | 08/23/2011 |
| 8000123 | Semiconductor memory device of open bit line type There is provided a semiconductor memory device that includes: a plurality of memory mats each including a plurality of word lines, a plurality of bit lines, a plurality of memory cells each located at an intersection between the word line and the bit line, and at l... | 08/16/2011 |
| 7995366 | Homogenous cell array A system for terminating a homogenous cell array is disclosed. A preferred embodiment comprises a plurality of homogenous cells arranged in rows and columns to form the homogenous cell array, wherein a first homogenous cell of each column is electrically differently... | 08/09/2011 |
