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Microwave Oven With Removable Storage Cassette in Dashboard of Motor Vehicle
A microwave oven adapted for use within a motor vehicle dashboard area. The microwave oven has a removable storage cassette, and slidable platforms for securing and serving containers of beverages and foods.
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| Number | Title | Issue Date |
| 7196921 | High-speed and low-power differential non-volatile content addressable memory cell and array A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or... | 03/27/2007 |
| 7196922 | Programmable priority encoder A programmable priority encoder is disclosed for use with the device such as a Content Addressable Memory (CAM) device having a plurality of array objects to be encoded in binary and arranged in row and columns. Match lines are adapted to be connected to a plurality... | 03/27/2007 |
| 7193876 | Content addressable memory (CAM) arrays having memory cells therein with different susceptibilities to soft errors A CAM array has at least one row therein containing a plurality of memory cells with different susceptibilities to soft errors. The memory cells having reduced susceptibilities to soft errors include those used in check bit cells and/or CAM cells containing valid bi... | 03/20/2007 |
| 7193877 | Content addressable memory with reduced test time A CAM device having internal circuitry to reduce test time through parallel test setup and parallel pass/fail result generation. A plurality of match results is generated in parallel within a plurality of CAM blocks of the CAM device in response to a search instruct... | 03/20/2007 |
| 7194593 | Memory hub with integrated non-volatile memory A memory hub having an integrated non-volatile memory for storing configuration information is provided. The memory hub includes a high-speed interface for receiving memory access requests, a non-volatile memory having memory configuration information stored therein... | 03/20/2007 |
| 7193874 | Content addressable memory device A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the ind... | 03/20/2007 |
| 7193875 | Cache hit logic of cache memory A cache hit logic for determining whether data required by a processor is stored in a cache memory includes a dummy cell string that operates the same as a sense amplifier for sensing a tag address stored in a tag memory cell array and a comparison logic for determi... | 03/20/2007 |
| 7191114 | System and method for evaluating character sets to determine a best match encoding a message An evaluator system accepts input textual messages in unknown languages and assesses which character sets, corresponding to languages, matches that message. Textual messages whose individual characters are encoded in 16 bit Unicode or other universal format are pars... | 03/13/2007 |
| 7190209 | Low-power high-performance integrated circuit and related methods An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on an... | 03/13/2007 |
| 7191291 | Microprocessor with variable latency stack cache A variable latency cache memory is disclosed. The cache memory includes a plurality of storage elements for storing stack memory data in a first-in-first-out manner. The cache memory distinguishes between pop and load instruction requests and provides pop data faste... | 03/13/2007 |
| 7191280 | Content addressable memories (CAMs) based on a binary CAM and having at least three states Content addressable memories are disclosed that provide at least three states and are based on existing binary CAM devices. A higher order CAM having at least three states comprises a binary CAM having two binary bits; and a logic circuit to configure the two binary... | 03/13/2007 |
| 7188211 | Block programmable priority encoder in a CAM A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical... | 03/06/2007 |
| 7187204 | Circuit for inspecting semiconductor device and inspecting method It is configured by plurality of NAND circuits connected in series through a plurality of inverters, and a plurality of NOR circuits connected in series through the plurality of inverters. Each of a plurality of source signal lines provided in a pixel portion is con... | 03/06/2007 |
| 7188219 | Buffer control system and method for a memory system having outstanding read and write request buffers A memory controller and method for managing the issuance of read and write requests to a system memory is provided. The number of outstanding read requests and write requests issued to the system memory are separately monitored and further issuance of read and write... | 03/06/2007 |
| 7187571 | Method and apparatus for CAM with reduced cross-coupling interference A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed. ... | 03/06/2007 |
| 7187570 | Content addressable memory architecture providing improved speed This invention provides, in an exemplary embodiment, a Content Addressable Memory (“CAM”) architecture providing improved speed by performing mutually exclusive operations in first state of a clock cycle and by performing at least one operation, dependent on at ... | 03/06/2007 |
| 7187608 | System and method for controlling the access and refresh of a memory The present invention provides a memory and memory control system wherein, except for one case noted below, the main memory gives priority to read or write operations over refresh operations. On the other hand, the cache memory give priority to the refresh operation... | 03/06/2007 |
| 7185141 | Apparatus and method for associating information values with portions of a content addressable memory (CAM) device According to one embodiment, a content addressable memory (CAM) device (100) may include a number of CAM entry sets (102-0 and 102-1), each of which includes multiple CAM entries. CAM (100) may also include multiple programm... | 02/27/2007 |
| 7185196 | Key caching system A key-caching system retrieves actively used keys from a relatively fast cache memory for fast processing of wireless communications. Additional keys are stored in relatively slow system memory that has high storage capacity. As keys become needed for active use, th... | 02/27/2007 |
| 7185175 | Configurable bi-directional bus for communicating between autonomous units Processing units (PUs) are coupled with a gated bi-directional bus structure that allows the PUs to be cascaded. Each PUn has communication logic and function logic. Each PUn is physically coupled to two other PUs, a PUp and a PUf. The communication logic receives L... | 02/27/2007 |
| 7184352 | Memory system and method using ECC to achieve low power refresh Rows of DRAM memory cells are refreshed at either a relatively high rate during normal operation or a relatively slow rate in a reduced power refresh mode. Prior to refreshing the rows of memory cells, the data are read from the memory cells, and corresponding syndr... | 02/27/2007 |
| 7185293 | Universal hardware device and method and tools for use therewith A universal hardware device including at least one plurality of cells for storing data; and at least one programmable matrix coupled to the at least one plurality of cells, whereby a plurality of hardware applications may be implemented by selectively storing data i... | 02/27/2007 |
| 7181568 | Content addressable memory to identify subtag matches The disclosure includes a description of a content addressable memory (CAM) that includes at least one tag input and at least one random access memory. The CAM also includes circuitry to perform multiple read operations of the at least one random access memory with ... | 02/20/2007 |
| 7180819 | Converting dual port memory into 2 single port memories A circuit is configured as a splittable duplex memory cell or as a joinable single port memory pair based on the state of a programming layer. The programming layer has two states. In one state, the programming layer configures the circuit as a joinable single port ... | 02/20/2007 |
| 7180803 | Data compression read mode for memory testing Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indicati... | 02/20/2007 |
| 7181567 | Hitless restart of access control module Performing selective update of a content addressable memory (CAM) following restart of an access control module (ACM) at a network node involves maintaining a restart CAM entry database in shared memory. When the ACM restarts, instead of reentering all CAM entries i... | 02/20/2007 |
| 7180820 | Integrated semiconductor memory comprising at least one word line and comprising a multiplicity of memory cells An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical po... | 02/20/2007 |
| 7180795 | Method of sensing an EEPROM reference cell An array of memory cells having a predetermined group of storage cells, arranged in a row, also have an arrangement of one or more reference cells fabricated to be adjacent to or proximate to the row of storage cells. The reference cells are written to, erased, or p... | 02/20/2007 |
| 7181584 | Dynamic command and/or address mirroring system and method for memory modules A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored configuration with mirrored terminals of memory devices on opposite su... | 02/20/2007 |
| 7181637 | Packet processing system and method for a data transfer node with time-limited packet buffering in a central queue A method and system are provided for processing data packets at a data-transfer network node. The method and system include determining a length of time that a packet has been buffered at the node by associating a timer with each data packet received and buffered in... | 02/20/2007 |
| 7180522 | Apparatus and method for distributed memory control in a graphics processing system A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memor... | 02/20/2007 |
| 7180328 | Apparatus and method for large hardware finite state machine with embedded equivalence classes A programmable finite state machine (FSM) includes, in part, a first address calculation logic block, a first lookup table, a second address calculation logic block, and a second lookup table. The first address calculation logic block generates an address for the fi... | 02/20/2007 |
| 7181587 | Mapping an arbitrary number of contiguous memory pages at an arbitrary alignment Virtual memory is mapped to physical memory in a computerized system. Two or more contiguous pages in virtual memory to be mapped to physical memory are identified, and the size in pages of the two or more contiguous pages is determined. An alignment in pages is det... | 02/20/2007 |
| 7176505 | Electromechanical three-trace junction devices Three trace electromechanical circuits and methods of using same. A circuit includes first and second electrically conductive elements with a nanotube ribbon (or other electromechanical elements) disposed therebetween. An insulative layer is disposed on one of the f... | 02/13/2007 |
| 7177853 | Cache management via statistically adjusted time stamp queue Described are techniques and criteria used in connection with cache management. The cache may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associate control slot that includes groups of ... | 02/13/2007 |
| 7177981 | Method and system for cache power reduction A method and system is disclosed for minimizing data array accesses during a read operation in a cache memory. The cache memory has one or more tag arrays and one or more data arrays. After accessing each tag array, a selected data array is identified, and subsequen... | 02/13/2007 |
| 7177201 | Negative bias temperature instability (NBTI) preconditioning of matched devices An accumulated data-dependent post-manufacture shift in a characteristic of one or more of a pair of matched devices within an integrated circuit may cause a mismatch in the characteristic between the pair of matched devices. This mismatch may be reduced by precondi... | 02/13/2007 |
| 7177225 | Block redundancy implementation in heirarchical RAM'S The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines ... | 02/13/2007 |
| 7174409 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 02/06/2007 |
| 7173839 | Large scale integrated circuit and at speed test method thereof Disclosed are an apparatus and a method that at-speed-test a data cache included in a semiconductor integrated circuit by means of an on-chip memory having a size smaller than that of the data cache. A data cache has a first data storage area. An on-chip memory has ... | 02/06/2007 |
