Did You Know...
...that the inventor of the electric motor was a blacksmith named Thomas Davenport? Described as "a brilliantly unsuccessful inventor", Davenport invented the first rotary electric motor. In 1836 he headed out -- on foot -- from his Vermont home to file a patent application at the Patent Office in Washington, D.C. By the time he got there, he had squandered away his money and couldn't afford the $30 filing fee so he turned around and went home. When he later mailed in his application with money he'd raised, the Patent office was destroyed in a fire. He did finally get credit for his invention on Feb. 5, 1837.
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| Number | Title | Issue Date |
| 7315936 | Enhanced boolean processor A set of processors, co-processors and processor cores having a Boolean logic unit, wherein the Boolean logic unit is operable, respectively, for performing the short-circuit evaluation of Conjunctive Normal Form Boolean expressions/operations, Disjunctive Normal Fo... | 01/01/2008 |
| 7313768 | Register file and method for designing a register file A register file includes a plurality of registers for storing therein data, a plurality of input ports for receiving therethrough the data to be stored in the registers, and a plurality of output ports for delivering therethrough the data stored in the registers. Ea... | 12/25/2007 |
| 7310345 | Empty indicators for weighted fair queues A scheduler for a network processor includes one or more scheduling queues. Each scheduling queue defines a respective sequence in which flows are to be serviced. A respective empty indicator is associated with each scheduling queue to indicate whether the respectiv... | 12/18/2007 |
| 7310748 | Memory hub tester interface and method for use thereof A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command,... | 12/18/2007 |
| 7310752 | System and method for on-board timing margin testing of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 12/18/2007 |
| 7307861 | Content addressable memory (CAM) cell bit line architecture A ternary content addressable memory (TCAM) cell (100) can include two memory elements (102-0 and 102-1) with a single bit line (106-0 and 106-1) per memory element. A TCAM cell (100) can also inc... | 12/11/2007 |
| 7307860 | Static content addressable memory cell A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second access transistors, each coupled between a data node of the latch and a respective data line. The gates of ... | 12/11/2007 |
| 7304874 | Compact ternary and binary CAM bitcell architecture with no enclosed diffusion areas Improved layouts of binary and ternary content addressable memory cells (BCAM and TCAM) are shown. A content addressable memory cell layout has a plurality of P+ diffusion areas and a plurality of N+ diffusion areas that do not enclose isolation regions and on which... | 12/04/2007 |
| 7304876 | Compare circuit for a content addressable memory cell A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of a mismatch. The speed of a CAM cell is generally inversely proportion... | 12/04/2007 |
| 7304873 | Method for on-the-fly error correction in a content addressable memory (CAM) and device therefor A CAM system (200) can include a number of entries (202-0 to 202-3) having one portion for storing a data value (e.g., E1) and another portion for storing a replicated data value (E1(REP)). For on-the-fly error correc... | 12/04/2007 |
| 7305519 | Error protection for associative memory entries and lookup operations performed thereon Error protection is provided for associative memory entries and lookup operations performed thereon. Protected associative memory entries are determined which include one or more protection bits. These protected entries are programmed into an associative memory, typ... | 12/04/2007 |
| 7304497 | Methods and apparatus for programmably powering down structured application-specific integrated circuits Methods and apparatus for programmably powering down a structured application-specific integrated circuit are provided. At least one of the programmable layers of the structured ASIC that frequently provides some programmability as between or among a small number of... | 12/04/2007 |
| 7304875 | Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same Search engine devices include a content addressable memory (CAM) core having a plurality of CAM array blocks therein and a control circuit. The control circuit, which is electrically coupled to the plurality of CAM array blocks, is configured to perform built-in sel... | 12/04/2007 |
| 7301792 | Apparatus and method of ordering state transition rules for memory efficient, programmable, pattern matching finite state machine hardware A programmable finite state machine (FSM) includes, in part, first and second memories, and a selection circuit coupled to each of the memories. Upon receiving a (k+m)-bit word representative of the k-bit input symbol and the m-bit current state, the first memory su... | 11/27/2007 |
| 7301832 | Compact column redundancy CAM architecture for concurrent read and write operations in multi-segment memory arrays A memory system incorporating redundancy utilizes a content addressable memory to monitor addresses during memory accesses. The content addressable memory provides a pointer to an alternate memory location when a previously determined faulty location is requested. R... | 11/27/2007 |
| 7302519 | Distributed content addressable memory The present invention provides a large capacity distributed content addressable memory (CAM) made up of a plurality of smaller CAMs interconnected on a high speed data bus. Each of the smaller CAMs is located at a local node on the data bus and configured to receive... | 11/27/2007 |
| 7301791 | Semiconductor device A semiconductor device capable of accessing to the memory with a high speed, and comprising a memory with a large capacity. The semiconductor device comprises a plurality of memory banks (Bank) 1 to 3 where the write cycle time is twice as long as the ... | 11/27/2007 |
| 7301850 | Content addressable memory (CAM) devices having bidirectional interface circuits therein that support passing word line and match signals on global word lines Content addressable memory devices include a bidirectional interface circuit configured to receive word line signals from a plurality of global word lines and pass match information from a selected one of a plurality of CAM arrays to the plurality of global word lin... | 11/27/2007 |
| 7299317 | Assigning prefixes to associative memory classes based on a value of a last bit of each prefix and their use including but not limited to locating a prefix and for maintaining a Patricia tree data structure Methods and apparatus are disclosed for maintaining and using entries in one or more associative memories. A last bit of a prefix is checked, and based on this result, the entry is placed into one of two classes of associative memory entries. The entry can then be i... | 11/20/2007 |
| 7298637 | Multiple match detection circuit and method A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising vo... | 11/20/2007 |
| 7298635 | Content addressable memory (CAM) cell with single ended write multiplexing A content addressable memory (CAM) cell circuit can include a match section that enables an impedance path coupled to a match line in response to a comparison between a data value and a compare data value. At least a first storage circuit can be connected to the mat... | 11/20/2007 |
| 7298636 | Packet processors having multi-functional range match cells therein A multi-functional match cell is responsive to first and second n-bit operands and configured so that the match cell operates as an n-bit range match cell when the first and second n-bit operands are equivalent, as an n-bit NOR-type CAM cell when the second n-bit op... | 11/20/2007 |
| 7296113 | Memory and power efficient mechanism for fast table lookup A method of implementing classification CAM functionality using primarily RAM cells is disclosed. The method offers significantly more table entries in a given area, or significantly less area for a given table size than conventional ternary CAMs. The method is much... | 11/13/2007 |
| 7295481 | Power saving by disabling cyclic bitline precharge A method and system of accessing memory cells within a dynamic hardware memory block operated with a bitline precharge circuit, in which differential read/write access operations are performed by activating complementary bitlines. A reduction in power dissipation is... | 11/13/2007 |
| 7296210 | Facilitating error detection for content addressable memory One embodiment of the disclosures made herein is an apparatus adapted to facilitate error detection for Content Addressable Memory (CAM) modules. The apparatus includes an input error detection module and an output error detection module. The input error detection m... | 11/13/2007 |
| 7295488 | Apparatus and methods for generating a column select line signal in semiconductor memory device An apparatus for generating a column select line signal in a semiconductor memory device includes a column select line signal generator configured to generate a column select line signal in response to a column select line enable signal. The column select line signa... | 11/13/2007 |
| 7295458 | Eight transistor SRAM cell with improved stability requiring only one word line An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs ... | 11/13/2007 |
| 7296114 | Control of memory and power efficient mechanism for fast table lookup A method of implementing classification CAM functionality using primarily RAM cells is disclosed. The method offers significantly more table entries in a given area, or significantly less area for a given table size than conventional ternary CAMs. The method is much... | 11/13/2007 |
| 7292487 | Independent polling for multi-page programming A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the memory banks. The cache memory is at least as large as the individual memory pages and is used to record the... | 11/06/2007 |
| 7292498 | Factored nanoscale multiplexer/demultiplexer circuit for interfacing nanowires with microscale and sub-microscale electronic devices Embodiments of the present invention are related to nanoscale multiplexers and demultiplexers that employ randomly fabricated interconnections between nanowire signal lines and microscale or sub-microscale address lines. A greater number of address lines than a mini... | 11/06/2007 |
| 7292162 | Data coding system and method A data coding system that compresses data and enables data, e.g., prefix addresses, to be represented with significantly fewer memory cells when compared to conventional coding systems. ... | 11/06/2007 |
| 7290092 | Runtime register allocator Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement... | 10/30/2007 |
| 7290085 | Method and system for flexible and efficient protocol table implementation A method for accessing a protocol table includes providing a content addressable protocol table comprising a plurality of entries, wherein each entry includes a key field and an output field, constructing a key value from a protocol input, associatively searching th... | 10/30/2007 |
| 7289347 | System and method for optically interconnecting memory devices A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable t... | 10/30/2007 |
| 7290083 | Error protection for lookup operations in content-addressable memory entries Error protection for lookup operations in a content-addressable memory (CAM) entries is disclosed. Values extended to include error protection or error protection fields are stored in CAM entries and a lookup operation is performed on a similarly extended lookup wor... | 10/30/2007 |
| 7289345 | CAM circuit and output method thereof A CAM circuit according to the present invention used for a cash memory and the like, wherein an address is obtained by designating a data, comprises a data compare unit for comparing a data stored in a memory unit to a data of a compare line in a state where a matc... | 10/30/2007 |
| 7286381 | Non-volatile and-type content addressable memory In order to speed up the search for a data item in a content addressable memory and to simplify the circuit structure of the memory having associated with each row of cells a ground control line, a ground line, a match control line, and with every row of cells there... | 10/23/2007 |
| 7286380 | Reconfigurable memory block redundancy to repair defective input/output lines An embodiment of the present invention is a technique to provide a reconfigurable repair circuit in a memory device. A table structure contains a plurality of entries, each entry having a defective address word and a redundant address word. The redundant address wor... | 10/23/2007 |
| 7286382 | Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between row segments to buffer signals on adjacent dataline segments. A contr... | 10/23/2007 |
| 7287120 | Associative memory and its retrieving method and router and network system An associative memory 4 for primary searching operation of an associative memory 23 supplies a valid state to a primary match line 13 corresponding to storage data coincident with search data 10 taking mask information into account, and s... | 10/23/2007 |
