Did You Know...
...that the video game, Pong, was invented by a guy who graduated at the bottom of his engineering class? Nolan Bushnell spent more time running the games at a local amusement park than he did on his studies at the University of Utah. His dreams of working for Disney's amusement empire were dashed when the company wouldn't hire him. Taking a boring job, Nolan daydreamed about electronic versions of popular games. He invented Pong, the first video game, and went on to found Atari Co.
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| Number | Title | Issue Date |
| 7143231 | Method and apparatus for performing packet classification for policy-based packet routing A method and apparatus for performing packet classification in a digital signal processor for policy-based packet routing. For one embodiment, the digital signal processor includes a policy statement table for storing policy statements. Each policy statement has ass... | 11/28/2006 |
| 7143239 | Cache structure and methodology A cache structure comprising a plurality of tag arrays and a plurality of data arrays, the tag arrays each configured to point to lines of data in multiple ones of the plurality of data arrays, wherein multiple tag arrays are searched in parallel for data that may b... | 11/28/2006 |
| 7142464 | Apparatus and methods for multi-level sensing in a memory array A method for sensing a signal received from an array cell within a memory array, the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array, and comparing the analog voltage Vddr with a... | 11/28/2006 |
| 7142547 | Scheduling device and cell communication device A scheduling device and a cell communication device capable of reducing a total storage region required for a scheduling function. Cell output control is performed by the scheduling function. The scheduling device includes a content addressable memory having queues ... | 11/28/2006 |
| 7139866 | CAM with automatic writing to the next free address A method and apparatus for automatically writing non-matching data to a non-valid location within a Content Addressable Memory (CAM) is disclosed. The non-valid locations are determined simultaneously with a search process for a matching address, so that in the even... | 11/21/2006 |
| 7139204 | Method and system for testing a dual-port memory at speed in a stressed environment A method and system for testing a multi-port memory cell are described. According to one embodiment of the invention, a multi-port memory device comprises an array of multi-port memory cells. Accordingly, each multi-port memory cell is connected to one word-line and... | 11/21/2006 |
| 7139190 | Single event upset tolerant memory cell layout Half cells of single-event-upset-tolerant memory cells are offset by at least two rows in a memory array. Offsetting the half cells separates them to avoid simultaneous damage to both half cells from a high-energy particle that could otherwise alter multiple nodes a... | 11/21/2006 |
| 7139852 | Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing A method and system transfer read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations of the memory device. The method includes placing a sequence of read data words on the data bus and apply... | 11/21/2006 |
| 7139877 | Microprocessor and apparatus for performing speculative load operation from a stack memory cache A cache memory for performing fast speculative load operations is disclosed. The cache memory caches stack data in a LIFO manner and stores both the virtual and physical address of the cache lines stored therein. The cache compares a load instruction virtual address... | 11/21/2006 |
| 7139182 | Cutting CAM peak power by clock regioning A CAM device architecture where CAM cells are divided into at least two arrays and each array is operated in a different clock domain so that at no time are the arrays simultaneously drawing maximum power. By dividing the CAM array into a plurality of arrays and sta... | 11/21/2006 |
| 7139909 | Technique for system initial program load or boot-up of electronic devices and systems A means for minimizing time for a system/device initial program load (IPL) in a system that will not support instruction prefetching when executing IPL code out of non-volatile memory. The IPL code is organized into a first portion and second portion. The first port... | 11/21/2006 |
| 7136961 | Method and apparatus for wide word deletion in content addressable memories A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all success... | 11/14/2006 |
| 7136960 | Hardware hashing of an input of a content addressable memory (CAM) to emulate a wider CAM An integrated circuit chip is provided having a port for receiving a character string. A hardware hashing circuit on the integrated circuit chip is configured to perform a hashing function on the character string, thereby creating a hashed output value. A binary con... | 11/14/2006 |
| 7136984 | Low power cache architecture In a processor cache, cache circuits are mapped into one or more logical modules. Each module may be powered down independently of other modules in response to microinstructions processed by the cache. Power control may be applied on a microinstruction-by-microinstr... | 11/14/2006 |
| 7136990 | Fast POP operation from RAM cache using cache row value stack A method and apparatus for performing a fast pop operation from a random access cache is disclosed. The apparatus includes a stack onto which is pushed the row and way of push instruction data stored into the cache. When a pop instruction is encountered, the apparat... | 11/14/2006 |
| 7137024 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 11/14/2006 |
| 7136958 | Multiple processor system and method including multiple memory hub modules A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors ... | 11/14/2006 |
| 7136006 | Systems and methods for mismatch cancellation in switched capacitor circuits Various circuits, systems and methods are disclosed for providing double-sampling sigma-delta modulator circuits. For example, circuits are disclosed that include an amplifier with an integrating capacitor, a switched capacitor conversion element that includes a sin... | 11/14/2006 |
| 7136308 | Efficient method of data transfer between register files and memories A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass gate, at least one driver and a bit line. The at least one pass gate and... | 11/14/2006 |
| 7133972 | Memory hub with internal cache and/or memory access prediction A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to ... | 11/07/2006 |
| 7133991 | Method and system for capturing and bypassing memory transactions in a hub-based memory system A memory hub includes a reception interface that receives data words and captures the data words in response to a first clock signal in a first time domain. The interface also provides groups of the captured data words on an output in response to a second clock sign... | 11/07/2006 |
| 7133302 | Low power content addressable memory A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled ... | 11/07/2006 |
| 7133316 | Program/erase method for P-channel charge trapping memory device A method of operating a memory device is disclosed, wherein the memory device includes an n-type substrate and a plurality of memory cells formed thereon, each memory cell corresponding to a word line, a first bit line, and second bit line, and including a first bit... | 11/07/2006 |
| 7130206 | Content addressable memory cell including resistive memory elements A content addressable memory cell is described. In one embodiment, the content addressable memory cell includes first and second resistive memory elements being coupled in a first series connection and being connected between a first potential value and a second pot... | 10/31/2006 |
| 7130230 | Systems for built-in-self-test for content addressable memories and methods of operating the same An improved Built-In-Self-Test (BIST) architecture for Content Addressable Memory (CAM) devices, including a bit scanner for reading out the contents of the matchlines of the CAM cells as a serial bit stream; a bit transition detector that detects and determines the... | 10/31/2006 |
| 7130236 | Low power delay controlled zero sensitive sense amplifier In one embodiment of the invention an integrated circuit is provided including a sense amplifier to read data from a memory cell that has a first transfer gate, a second transfer gate, a comparator, and a control circuit. The first transfer gate has a first pole cou... | 10/31/2006 |
| 7130312 | Packet processing apparatus, packet processing method, and packet exchange A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing p... | 10/31/2006 |
| 7126946 | Dual key controlled content addressable memory for accessing packet switch data buffer for multicasting data packets A data management architecture for a high speed packet switch has a dual key-based content addressable memory (CAM)-based buffer access control mechanism that stores relatively long data packets for delivery to multiple output ports of the switch. The CAM stores mul... | 10/24/2006 |
| 7126837 | Interlocking memory/logic cell layout and method of manufacture A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell (102, 104) can include a pair of memory areas to store data (106-0/106-1, 106-2/106-3), and a logic por... | 10/24/2006 |
| 7126834 | Sense amplifier architecture for content addressable memory device A content addressable memory (CAM) device (200) can equalize a potential between a match line (202) and corresponding pseudo-supply (PVSS) line (204) in a pre-sense operation. In a sense operation, a sensing device (P4) can determine a ma... | 10/24/2006 |
| 7127559 | Caching of dynamic arrays Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic overlays. According to one embodiment, the device includes a plurality of memory cells and at least one regi... | 10/24/2006 |
| 7126398 | Method and an apparatus to generate static logic level output A method and an apparatus to generate static logic level outputs without a direct connection from a MOS transistor gate to either a power supply or ground supply are described. The apparatus may include a first circuit comprising a static logic level output. The app... | 10/24/2006 |
| 7123500 | 1P1N 2T gain cell A two-transistor DRAM cell includes an NMOS device and a PMOS device coupled to the NMOS device. ... | 10/17/2006 |
| 7124268 | Sorting method and apparatus using a CAM Method and apparatus for using a Content Addressable Memory for sorting a plurality of data items is presented. The data items to be sorted are stored in the Content Addressable Memory. A plurality of bit-by-bit burst searches are performed on the contents of the Co... | 10/17/2006 |
| 7123496 | L0 cache alignment circuit A L0 cache is provided that includes a plurality of memory cells, full swing signal bit lines coupled to the plurality of memory cells to output full swing data signals, small signal global bit lines coupled to the full swing signal bit lines to provide small signal... | 10/17/2006 |
| 7120732 | Content addressable memory structure A structure, apparatus and method for reducing the power requirement of CAM memories, where the memory cells of the memory array are divided into groups of rows of multiple memory segments. Each memory segment has its own search driver and is searched separately. Th... | 10/10/2006 |
| 7120727 | Reconfigurable memory module and method A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously addr... | 10/10/2006 |
| 7120731 | CAM-based search engines that support pipelined multi-database search operations using replacement search key segments CAM-based search engines may be configured to support multiple databases within a CAM core. These databases may represent tables for different applications, which can be searched sequentially in response to a single indirect instruction that is loaded during a contr... | 10/10/2006 |
| 7120743 | Arbitration system and method for memory responses in a hub-based memory system A memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses, and a buffered queue coupled to the bypass path that stores downstream memory responses from the bypass path. A multiplexer is coupled to t... | 10/10/2006 |
| 7119941 | Input output matching in optical processing The invention relates to determining a matching between discrete optical elements, such as an SLM and a CCD, and continuous optical systems, subsystems and/or elements, such as Fourier lens and individual lenslet of lenslet arrays. Exemplary processing performed by ... | 10/10/2006 |
